Hello there!
I ported the WebServer example from MicroBlaze Development Kit, Spartan -3E 1600E Edition to spartan 3e starter kit (revD), it seems to work until I want to open a webpage on the embedded webserver...
--- I made a new project with the required peripherals, and I added the input buffer and LCD core to the projects, from the .mhs and .mss files I made those modifications which is required (and in the .ucf too). The TestApp_Mem is OK, but when I run the TestApp_Peripheral, It seems that the interrupt controller and the timer not work (with interrupt)...
What do you think, what would be the problem with it? (I'm a beginner with not too much experience)
I send the MHS and MSS files:
# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4 # Fri Aug 31 21:24:07 2007 # Target Board: Xilinx Spartan-3E Starter Board Rev D # Family: spartan3e # Device: XC3S500e # Package: FG320 # Speed Grade: -4 # Processor: Microblaze # System clock frequency: 66.666667 MHz # Debug interface: On-Chip HW Debug Module # Data Cache: 8 KB # Instruction Cache: 8 KB # On Chip Memory : 8 KB # Total Off Chip Memory : 80 MB # - FLASH_16Mx8 = 16 MB # - DDR_SDRAM_32Mx16 = 64 MB # ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:7] PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3] PORT fpga_0_FLASH_16Mx8_Mem_OEN_pin = fpga_0_FLASH_16Mx8_Mem_OEN, DIR = O PORT fpga_0_FLASH_16Mx8_Mem_CEN_pin = fpga_0_FLASH_16Mx8_Mem_CEN, DIR = O, VEC = [0:0] PORT fpga_0_FLASH_16Mx8_Mem_WEN_pin = fpga_0_FLASH_16Mx8_Mem_WEN, DIR = O PORT fpga_0_FLASH_16Mx8_emc_ben_gnd_pin = net_gnd, DIR = O PORT fpga_0_FLASH_16Mx8_Mem_A_pin = fpga_0_FLASH_16Mx8_Mem_A, DIR = O, VEC = [8:31] PORT fpga_0_FLASH_16Mx8_Mem_DQ_pin = fpga_0_FLASH_16Mx8_Mem_DQ, DIR = IO, VEC = [0:7] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr, DIR = O, VEC = [0:12] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr, DIR = O, VEC = [0:1] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DM, DIR = O, VEC = [0:1] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS, DIR = IO, VEC = [0:1] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ, DIR = IO, VEC = [0:15] PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 66666667 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
50000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST PORT LCD_E_pin = opb_lcd_0_LCD_E, DIR = O PORT LCD_RW_pin = opb_lcd_0_LCD_RW, DIR = O PORT LCD_RS_pin = opb_lcd_0_LCD_RS, DIR = O PORT LCD_DB_pin = opb_lcd_0_LCD_DB, DIR = O, VEC = [3:0]BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 4.00.b PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_USE_ICACHE = 1 PARAMETER C_CACHE_BYTE_SIZE = 8192 PARAMETER C_USE_DCACHE = 1 PARAMETER C_DCACHE_BYTE_SIZE = 8192 PARAMETER C_ICACHE_USE_FSL = 1 PARAMETER C_DCACHE_USE_FSL = 1 PARAMETER C_ICACHE_BASEADDR = 0x24000000 PARAMETER C_ICACHE_HIGHADDR = 0x27ffffff PARAMETER C_DCACHE_BASEADDR = 0x24000000 PARAMETER C_DCACHE_HIGHADDR = 0x27ffffff BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb BUS_INTERFACE IXCL = ixcl BUS_INTERFACE DXCL = dxcl PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s PORT Interrupt = Interrupt PORT RESET = microblaze_rst END
BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = bus_rst_0 PORT OPB_Clk = sys_clk_s END
BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE SOPB = mb_opb PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_REG_EN_0 = DBG_REG_EN_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_UPDATE_0 = DBG_UPDATE_s PORT OPB_Rst = periph_rst_0 PORT Debug_SYS_Rst = Debug_SYS_Rst PORT Debug_Rst = Debug_Rst PORT OPB_Clk = sys_clk_s END
BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = bus_rst_1 PORT LMB_Clk = sys_clk_s END
BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = bus_rst_2 PORT LMB_Clk = sys_clk_s END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port PORT LMB_Rst = periph_rst_1 END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port PORT LMB_Rst = periph_rst_2 END
BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port PORT BRAM_Rst_A = periph_rst_3 PORT BRAM_Rst_B = periph_rst_4 END
BEGIN opb_uartlite PARAMETER INSTANCE = RS232_DCE PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 115200 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 66666667 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE SOPB = mb_opb PORT Interrupt = RS232_DCE_Interrupt PORT RX = fpga_0_RS232_DCE_RX PORT TX = fpga_0_RS232_DCE_TX PORT OPB_Rst = periph_rst_5 PORT OPB_Clk = sys_clk_s END
BEGIN opb_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER HW_VER = 3.01.b PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x4000ffff BUS_INTERFACE SOPB = mb_opb PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out PORT OPB_Clk = sys_clk_s PORT OPB_Rst = periph_rst_6 END
BEGIN opb_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER HW_VER = 3.01.b PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x40020000 PARAMETER C_HIGHADDR = 0x4002ffff BUS_INTERFACE SOPB = mb_opb PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in PORT OPB_Clk = sys_clk_s PORT OPB_Rst = periph_rst_7 END
BEGIN opb_emc PARAMETER INSTANCE = FLASH_16Mx8 PARAMETER HW_VER = 2.00.a PARAMETER C_OPB_CLK_PERIOD_PS = 14999 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_MAX_MEM_WIDTH = 8 PARAMETER C_MEM0_WIDTH = 8 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 PARAMETER C_SYNCH_MEM_0 = 0 PARAMETER C_TCEDV_PS_MEM_0 = 110000 PARAMETER C_TWC_PS_MEM_0 = 110000 PARAMETER C_TAVDV_PS_MEM_0 = 110000 PARAMETER C_TWP_PS_MEM_0 = 70000 PARAMETER C_THZCE_PS_MEM_0 = 35000 PARAMETER C_TLZWE_PS_MEM_0 = 15000 PARAMETER C_MEM0_BASEADDR = 0x22000000 PARAMETER C_MEM0_HIGHADDR = 0x22ffffff BUS_INTERFACE SOPB = mb_opb PORT Mem_A = fpga_0_FLASH_16Mx8_Mem_A_split PORT Mem_DQ = fpga_0_FLASH_16Mx8_Mem_DQ PORT Mem_OEN = fpga_0_FLASH_16Mx8_Mem_OEN PORT Mem_WEN = fpga_0_FLASH_16Mx8_Mem_WEN PORT Mem_CEN = fpga_0_FLASH_16Mx8_Mem_CEN PORT OPB_Clk = sys_clk_s PORT OPB_Rst = periph_rst_8 END
BEGIN mch_opb_ddr PARAMETER INSTANCE = DDR_SDRAM_32Mx16 PARAMETER HW_VER = 1.00.c PARAMETER C_INCLUDE_OPB_BURST_SUPPORT = 0 PARAMETER C_MCH_OPB_CLK_PERIOD_PS = 14999 PARAMETER C_REG_DIMM = 0 PARAMETER C_DDR_TMRD = 15000 PARAMETER C_DDR_TWR = 15000 PARAMETER C_DDR_TWTR = 1 PARAMETER C_DDR_TRAS = 40000 PARAMETER C_DDR_TRC = 65000 PARAMETER C_DDR_TRFC = 75000 PARAMETER C_DDR_TRCD = 20000 PARAMETER C_DDR_TRRD = 15000 PARAMETER C_DDR_TRP = 20000 PARAMETER C_DDR_TREFI = 7800000 PARAMETER C_DDR_DWIDTH = 16 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 10 PARAMETER C_MCH0_ACCESSBUF_DEPTH = 16 PARAMETER C_MCH0_RDDATABUF_DEPTH = 0 PARAMETER C_XCL0_LINESIZE = 4 PARAMETER C_XCL0_WRITEXFER = 0 PARAMETER C_MCH1_ACCESSBUF_DEPTH = 16 PARAMETER C_MCH1_RDDATABUF_DEPTH = 0 PARAMETER C_XCL1_LINESIZE = 4 PARAMETER C_XCL1_WRITEXFER = 1 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_DDR_ASYNC_SUPPORT = 1 PARAMETER C_NUM_CLK_PAIRS = 1 PARAMETER C_MEM0_BASEADDR = 0x24000000 PARAMETER C_MEM0_HIGHADDR = 0x27ffffff BUS_INTERFACE SOPB = mb_opb BUS_INTERFACE MCH0 = ixcl BUS_INTERFACE MCH1 = dxcl PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx16_DDR_DM PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ PORT Device_Clk90_in = clk_90_s PORT Device_Clk90_in_n = clk_90_n_s PORT Device_Clk = sys_clk_s PORT Device_Clk_n = sys_clk_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s PORT MCH_OPB_Rst = periph_rst_9 END
BEGIN opb_ethernet PARAMETER INSTANCE = Ethernet_MAC PARAMETER HW_VER = 1.04.a PARAMETER C_DMA_PRESENT = 1 PARAMETER C_IPIF_RDFIFO_DEPTH = 32768 PARAMETER C_IPIF_WRFIFO_DEPTH = 32768 PARAMETER C_OPB_CLK_PERIOD_PS = 14999 PARAMETER C_BASEADDR = 0x40c00000 PARAMETER C_HIGHADDR = 0x40c0ffff BUS_INTERFACE SOPB = mb_opb PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_O PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_O PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data PORT OPB_Clk = sys_clk_s PORT OPB_Rst = periph_rst_10 END
BEGIN opb_timer PARAMETER INSTANCE = opb_timer_1 PARAMETER HW_VER = 1.00.b PARAMETER C_COUNT_WIDTH = 32 PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_BASEADDR = 0x41c00000 PARAMETER C_HIGHADDR = 0x41c0ffff BUS_INTERFACE SOPB = mb_opb PORT Interrupt = opb_timer_1_Interrupt PORT OPB_Clk = sys_clk_s PORT OPB_Rst = periph_rst_12 END
BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x41200000 PARAMETER C_HIGHADDR = 0x4120ffff PARAMETER C_NUM_INTR_INPUTS = 2 BUS_INTERFACE SOPB = mb_opb PORT Irq = Interrupt PORT Intr = RS232_DCE_Interrupt & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt PORT OPB_Rst = periph_rst_13 END
BEGIN util_bus_split PARAMETER INSTANCE = FLASH_16Mx8_util_bus_split_1 PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE_IN = 32 PARAMETER C_LEFT_POS = 0 PARAMETER C_SPLIT = 8 PORT Sig = fpga_0_FLASH_16Mx8_Mem_A_split PORT Out2 = fpga_0_FLASH_16Mx8_Mem_A END
BEGIN util_vector_logic PARAMETER INSTANCE = sysclk_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = sys_clk_s PORT Res = sys_clk_n_s END
BEGIN util_vector_logic PARAMETER INSTANCE = clk90_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = clk_90_s PORT Res = clk_90_n_s END
BEGIN util_vector_logic PARAMETER INSTANCE = ddr_clk90_inv PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE = 1 PARAMETER C_OPERATION = not PORT Op1 = ddr_clk_90_s PORT Res = ddr_clk_90_n_s END
BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_DIVIDE = 3 PARAMETER C_CLKFX_MULTIPLY = 4 PARAMETER C_CLKIN_PERIOD = 20.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLKFX = sys_clk_s PORT CLK0 = dcm_0_FB PORT CLKFB = dcm_0_FB PORT RST = net_gnd PORT LOCKED = dcm_0_lock END
BEGIN dcm_module PARAMETER INSTANCE = dcm_1 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 15.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 0 PORT CLKIN = sys_clk_s PORT CLK90 = clk_90_s PORT CLK0 = dcm_1_FB PORT CLKFB = dcm_1_FB PORT RST = dcm_0_lock PORT LOCKED = dcm_1_lock END
BEGIN dcm_module PARAMETER INSTANCE = dcm_2 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLK90_BUF = TRUE PARAMETER C_CLKIN_PERIOD = 15.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 0 PORT CLKIN = ddr_feedback_s PORT CLK90 = ddr_clk_90_s PORT CLK0 = dcm_2_FB PORT CLKFB = dcm_2_FB PORT RST = dcm_1_lock PORT LOCKED = dcm_2_lock END
BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_NUM_BUS_RST = 3 PARAMETER C_NUM_PERP_RST = 14 PORT Dcm_locked = dcm_2_lock PORT Bus_Struct_Reset = bus_rst_0 & bus_rst_1 & bus_rst_2 PORT Peripheral_Reset = periph_rst_0 & periph_rst_1 & periph_rst_2 & periph_rst_3 & periph_rst_4 & periph_rst_5 & periph_rst_6 & periph_rst_7 & periph_rst_8 & periph_rst_9 & periph_rst_10 & periph_rst_11 & periph_rst_12 & periph_rst_13 PORT Slowest_sync_clk = sys_clk_s PORT Ext_Reset_In = sys_rst_s PORT Aux_Reset_In = net_gnd PORT Core_Reset_Req = Debug_Rst PORT Chip_Reset_Req = net_gnd PORT System_Reset_Req = Debug_SYS_Rst PORT Rstc405resetcore = microblaze_rst END
BEGIN input_buf PARAMETER INSTANCE = in_buf0 PARAMETER HW_VER = 1.00.a PARAMETER DWIDTH = 2 PORT I = fpga_0_Ethernet_MAC_PHY_tx_clk & fpga_0_Ethernet_MAC_PHY_rx_clk PORT O = fpga_0_Ethernet_MAC_PHY_tx_clk_O & fpga_0_Ethernet_MAC_PHY_rx_clk_O END
BEGIN opb_lcd PARAMETER INSTANCE = char_lcd PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x73a00000 PARAMETER C_HIGHADDR = 0x73a0ffff BUS_INTERFACE SOPB = mb_opb PORT LCD_E = opb_lcd_0_LCD_E PORT LCD_RW = opb_lcd_0_LCD_RW PORT LCD_RS = opb_lcd_0_LCD_RS PORT LCD_DB = opb_lcd_0_LCD_DB PORT OPB_Clk = sys_clk_s PORT OPB_Rst = periph_rst_11 END
---------------------------------------------------------------------------------------------------------------------------------- system.mss:
PARAMETER VERSION = 2.2.0
BEGIN OS PARAMETER OS_NAME = xilkernel PARAMETER OS_VER = 3.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER sysintc_spec = opb_intc_0 PARAMETER stdout = RS232_DCE PARAMETER stdin = RS232_DCE PARAMETER config_debug_support = true PARAMETER config_sema = true PARAMETER max_sem_waitq = 100 PARAMETER max_sem = 25 PARAMETER config_time = true PARAMETER max_tmrs = 100 PARAMETER systmr_freq = 66666667 PARAMETER systmr_dev = opb_timer_1 PARAMETER max_readyq = 100 PARAMETER pthread_stack_size = 16384 PARAMETER max_pthreads = 100 PARAMETER static_pthread_table = ((serverThread,1)) END
BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.01.a PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar PARAMETER XMDSTUB_PERIPHERAL = debug_module PARAMETER CORE_CLOCK_FREQ_HZ = 50000000 END
BEGIN DRIVER PARAMETER DRIVER_NAME = opbarb PARAMETER DRIVER_VER = 1.02.a PARAMETER HW_INSTANCE = mb_opb END
BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.01.a PARAMETER HW_INSTANCE = debug_module END
BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlr END
BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlr END
BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.01.a PARAMETER HW_INSTANCE = RS232_DCE END
BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.01.a PARAMETER HW_INSTANCE = LEDs_8Bit END
BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.01.a PARAMETER HW_INSTANCE = DIP_Switches_4Bit END
BEGIN DRIVER PARAMETER DRIVER_NAME = emc PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = FLASH_16Mx8 END
BEGIN DRIVER PARAMETER DRIVER_NAME = sdram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = DDR_SDRAM_32Mx16 END
BEGIN DRIVER PARAMETER DRIVER_NAME = emac PARAMETER DRIVER_VER = 1.01.a PARAMETER HW_INSTANCE = Ethernet_MAC END
BEGIN DRIVER PARAMETER DRIVER_NAME = tmrctr PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = opb_timer_1 END
BEGIN DRIVER PARAMETER DRIVER_NAME = intc PARAMETER DRIVER_VER = 1.00.c PARAMETER HW_INSTANCE = opb_intc_0 END
BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = in_buf0 END
BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = char_lcd END
BEGIN LIBRARY PARAMETER LIBRARY_NAME = xilmfs PARAMETER LIBRARY_VER = 1.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER need_utils = true PARAMETER init_type = MFSINIT_IMAGE PARAMETER base_address = 0x25000000 PARAMETER numbytes = 319200 END
BEGIN LIBRARY PARAMETER LIBRARY_NAME = lwip PARAMETER LIBRARY_VER = 2.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER api_mode = SOCKETS_API PARAMETER memp_num_sys_timeout = 5 PARAMETER memp_num_tcp_seg = 510 PARAMETER mem_size = 65538 PARAMETER emac_instances = ((Ethernet_MAC,
0x01,0x02,0x03,0x04,0x05,0x06)) END