Latest threads in Field-Programmable Gate Arrays

VHDL Synthesis Error

Hello all, I am trying to implement a network adapter that sends small packets to and from FPGA boards using VHDL. I wa...

4 19yrs

ray.delvecchio

4 19yrs ray.delvecchio

LVDS pin placing on CYCLON II problem

Hi, I'm working on design with LVDS signals and when I'm trying to place LVDS inputs at dedicated pins I got : Error: N...

3 19yrs

gorskia

3 19yrs gorskia

Quick question for an Altera wizard

I have a verilog design on Spartan 3 which needs to move to Cyclone II. The design has 7 128x1 bit asynchronous ROMs us...

4 19yrs

nospam

4 19yrs nospam

Minimize power consumption

Hi. I have a question. I have a special y=f(x) function. It takes 32 bit at input and it have something at output. Func...

11 19yrs

drop669

11 19yrs drop669

Anyway to stop Altera Stratix II SignalTap data acquisition

I set the SignalTap memory depth to 16K and would like to collect exactly that many data points after the trigger. Howe...

1 19yrs

frankzhangee

1 19yrs frankzhangee

Help getting sdram running with EDK.

I've been struggling for weeks to get sdram to work correctly on a newly designed board. I was hoping that someone migh...

4 19yrs

johnblake2000

4 19yrs johnblake2000

Nios II -- Why does this error occur ?

When I Run the NiosII project, there is sometimes this error info. in the console: nios2-terminal: exiting due to ^D on...

1 19yrs

hezhikuan2007

1 19yrs hezhikuan2007

New keyword 'OIF' and its implications

Hi, 1. Based on the previous very benefitial discussions and my observation on the topics, I decide to recant the follo...

0 19yrs

wtxwtx

0 19yrs wtxwtx

RE: FPGA/VHDL digital Design permanent role - Oxford

Hi, I have a really exciting R&D role with a Media/Broadcast organisation in the Oxford area. If you have a solid backg...

0 19yrs

khomeyard

0 19yrs khomeyard

SRAM on Cyclone Devices

Target Device: CYCLONE My project allocates some RAM and initializes it by an Intel Hex File. The Simulator correctly s...

1 19yrs

me

1 19yrs me

How to simple convert a hex or mif file from Altera to Xilinx coe file?

Hi, How to simple convert a hex or mif file from Altera to Xilinx coe file? Do you know any little software? Regards Ber...

2 19yrs

esteban.bernard***spam***

2 19yrs esteban.bernard***spam***

[Nios II] How does the PIO Core generate a interrupt?

I have designed a counter, it works like this: when the counter reach a number , one of its output pins generate a high...

3 19yrs

hezhikuan2007

3 19yrs hezhikuan2007

Rocket IO clock

Hi there, I'm not very pleased reading the virtex 5 datasheet dealing with Rocket IO transcievers. In fact the Xilinx d...

1 19yrs

piclist9

1 19yrs piclist9

DDR Simulation via MIG

I am looking into a MIG-generated DDR SDRAM interface and am having trouble with the simulation. I can see the interfac...

2 19yrs

mottoblatto

2 19yrs mottoblatto

VCCAUX too high on a Spartan 3 design

Using linear adjustable regulators for VCCINT (1.25v), VCCIO (3.3v), and VCCAUX (2.5v). VCCINT and VCCIO are dead on, b...

10 19yrs

danielgkNOSPAM

10 19yrs danielgkNOSPAM

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