Quick question for an Altera wizard

How about using generic verilog constructs instead? Using primitives is only going to be a source of headaches when used for no particular reason as FPGA architectures evolve and designs need to be ported across device families or vendors.

Simply create an array of 7bits elements, initialize it to whatever your ROM's content has to be and use an index to access it. Pretty much any FPGA synthesis tool worth anything will be able to figure these out and do a satisfactory job in 99% of cases.

I only use primitives for stuff that cannot be inferred. The other defendable reasons to use primitives is for timing-critical and space-critical logic/paths. That aside, I think they should be avoided.

I can send you code that makes a nice fifo out of SRL16s on a Xilinx part (via inference, not with the coregen) and a huge mishmash of flops on an Altera part... If you use 10% of your FPGA you can be content to use perfectly portable source code. If you really need the best speed and density, you're stuck with generated modules that sometimes don't map well to other architectures.

I'd be interested in it if you don't mine

KJ

I'd be interested in it if you don't mind.

KJ