Rocket IO clock

Hi there,

I'm not very pleased reading the virtex 5 datasheet dealing with Rocket IO transcievers. In fact the Xilinx datasheets are not comprehensive and dificult to read.

Every transciever bank has two lanes and a differential clock. It seems the transciever can work with the regional clock too. See page 66 of the

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"There are three ways to drive the CLKIN port (see Figure 5-3): =B7 Using an external oscillator to drive GTP dedicated clock routing =B7 Using a clock from a neighboring GTP_DUAL tile through GTP dedicated clock routing =B7 Using a clock from inside the FPGA (GREFCLK)"

However the jitter requirements for the rocket IO clk is restrictive.

"GREFCLK clocking is not recommended for most designs because of the increased jitter introduced by the FPGA clock nets." Why the hell they keep it ?

Which will be your recommandation: using a suplementary low jitter LVDS clock for every Rocket IO transciever or one clock to 3+1+3 transcievers? If using a LVDS clock, one differential clock can be shared succesfully between multiple transcievers ? (see page 69 of the same datasheet). There is no information about the max jitter of such configuration for the longest clk (the third transciever away from the clk supply).

thank you very much, Vasile

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There is no significant performance difference between using the REFCLK pins associated with the same GTP_DUAL site and driving using the dedicated routing resources in the GTP_DUAL column up to 3 GTP_DUAL sites away from the input location. All of the GTP_DUAL datasheet values are based on the worst case conditions.

The 3rd choice of routing the input from a BUFG or BUFR source is available, but the datasheet performance specifications are not guaranteed in this configuration as jitter component of these nets are highly dependent on the specific design and operating conditions. If you find this unacceptable please do not use this option. There are designers that appreciate that this option is available and understand that they need to do additional verification that their final design meets their performance requirements.

Ed McGettigan

-- Xilinx Inc.

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Ed McGettigan

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