Field-Programmable Gate Arrays

Clock boundary crossing

What are the different ways of crossing clock boundaries. Is there any website with good information on that. Thanks Ami...

10 comments posted 18yrs

posted by axr0284

10 comments posted 18yrs posted by axr0284

Free downloadable PDF graph paper.

Dear All, I found this online and found it useful. Maybe you will too. http://incompetech.com/graphpaper/ Cheers, Syms.

4 comments posted 18yrs

posted by symon_brewer

4 comments posted 18yrs posted by symon_brewer

Is it possible to perform gate level simulation on a design without a reset?

Hi, If an Altera design does not have a reset, then what happens to the registers during gate level simulation? I assum...

11 comments posted 18yrs

posted by aclegg1986

11 comments posted 18yrs posted by aclegg1986

load/read/ commands assembly PowerPC. Help Needed!

Hello all, I am trying to load a 32bit data (word) from the PortB of a BRAM to a GPR (general purpose register) of the...

9 comments posted 18yrs

posted by lastval

9 comments posted 18yrs posted by lastval

Question about timing of Xilinx Core generated counter

Hi, I find a problem in the simulation of watchvhd example from Xilinx ISE 8.2 or 9.1. There is a Core generated counte...

0 comments posted 18yrs

posted by rxjwg98

0 comments posted 18yrs posted by rxjwg98

JTAG CPLD Configuration

Hello I have a Xilinx XCR3064 CPLD with its JTAG pins hooked up to some digital I/O pins on a uC. I intend to configure...

0 comments posted 18yrs

posted by nononono

0 comments posted 18yrs posted by nononono

REGARDING ILA in FPGA EDITOR

Hi all, I am using ISE 9.1I and Chipscope 9.1i. I tried to change some nets in ILA thorogh FPGA EDITOR ila command. It...

0 comments posted 18yrs

posted by mailmurali18

0 comments posted 18yrs posted by mailmurali18

FATAL ERROR ISE9.1i

Hi, i get this message when i run post & route: Starting Placer FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll...

2 comments posted 18yrs

posted by james.lbs

2 comments posted 18yrs posted by james.lbs

¡¾Nios II¡¿How Can I Find Out These Functions £¿

I'm a beginner in the Nios II System. When I learn the examples provided by Nios II IDE, I always see this type's funct...

3 comments posted 18yrs

posted by hezhikuan2007

3 comments posted 18yrs posted by hezhikuan2007

How to deal with the tempary coefficient in the FPGA design

In my FPGA design, I need a result of EXP(z: is complex) as a tempary coefficient for other calculations. I've known to...

0 comments posted 18yrs

posted by threeinchnail

0 comments posted 18yrs posted by threeinchnail

high bandwitch ethernet communication

Hello, In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and s...

15 comments posted 18yrs

posted by eliben

15 comments posted 18yrs posted by eliben

clock skew problems

Hi all, I've got a FPGA design with a lot of clocks! I know this is not really good, but I've to implement a microproce...

4 comments posted 18yrs

posted by michel.talon

4 comments posted 18yrs posted by michel.talon

EDK9.1 linux registration fails (vista ok)

Hi groups, is there any reason for edk 9.1 registration failure with linux (I use the same id that successfully register...

1 comments posted 18yrs

posted by rponsard

1 comments posted 18yrs posted by rponsard

warning 1780 shown while synthesis, in xilinx 6.3i

hi I am designing a generic arbiter . while synthesis the xilinx tool is giving warning WARNING:Xst:646 - Signal is ass...

1 comments posted 18yrs

posted by ankurrawat0612

1 comments posted 18yrs posted by ankurrawat0612

vnavigator problem

Hello all, I am working on merging code coverage results in Verification Navigator from TransEDA. I am encountering an...

0 comments posted 18yrs

posted by kris.koorndyk

0 comments posted 18yrs posted by kris.koorndyk