Latest threads in Field-Programmable Gate Arrays

ANNC: New Boundary-Scan Software

Dear All, Please have a look at Scanseer (http://www.scanseer.com), a new software for 'manual' boundary-scan testing....

5 19yrs

skswrus

5 19yrs skswrus

Problem locking a DCM driven by FX output of another DCM

I have a design with 3 DCMs. The first DCM generates 280 MHz out of 210 MHz. It is then divided by 2 and 4 in a PMCD. T...

16 19yrs

mbmsv

16 19yrs mbmsv

Clock boundary crossing

What are the different ways of crossing clock boundaries. Is there any website with good information on that. Thanks Ami...

10 19yrs

axr0284

10 19yrs axr0284

Free downloadable PDF graph paper.

Dear All, I found this online and found it useful. Maybe you will too. http://incompetech.com/graphpaper/ Cheers, Syms.

4 19yrs

symon_brewer

4 19yrs symon_brewer

Is it possible to perform gate level simulation on a design without a reset?

Hi, If an Altera design does not have a reset, then what happens to the registers during gate level simulation? I assum...

11 19yrs

aclegg1986

11 19yrs aclegg1986

load/read/ commands assembly PowerPC. Help Needed!

Hello all, I am trying to load a 32bit data (word) from the PortB of a BRAM to a GPR (general purpose register) of the...

9 19yrs

lastval

9 19yrs lastval

Question about timing of Xilinx Core generated counter

Hi, I find a problem in the simulation of watchvhd example from Xilinx ISE 8.2 or 9.1. There is a Core generated counte...

0 19yrs

rxjwg98

0 19yrs rxjwg98

JTAG CPLD Configuration

Hello I have a Xilinx XCR3064 CPLD with its JTAG pins hooked up to some digital I/O pins on a uC. I intend to configure...

0 19yrs

nononono

0 19yrs nononono

REGARDING ILA in FPGA EDITOR

Hi all, I am using ISE 9.1I and Chipscope 9.1i. I tried to change some nets in ILA thorogh FPGA EDITOR ila command. It...

0 19yrs

mailmurali18

0 19yrs mailmurali18

FATAL ERROR ISE9.1i

Hi, i get this message when i run post & route: Starting Placer FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll...

2 19yrs

james.lbs

2 19yrs james.lbs

¡¾Nios II¡¿How Can I Find Out These Functions £¿

I'm a beginner in the Nios II System. When I learn the examples provided by Nios II IDE, I always see this type's funct...

3 19yrs

hezhikuan2007

3 19yrs hezhikuan2007

How to deal with the tempary coefficient in the FPGA design

In my FPGA design, I need a result of EXP(z: is complex) as a tempary coefficient for other calculations. I've known to...

0 19yrs

threeinchnail

0 19yrs threeinchnail

high bandwitch ethernet communication

Hello, In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and s...

15 19yrs

eliben

15 19yrs eliben

clock skew problems

Hi all, I've got a FPGA design with a lot of clocks! I know this is not really good, but I've to implement a microproce...

4 19yrs

michel.talon

4 19yrs michel.talon

EDK9.1 linux registration fails (vista ok)

Hi groups, is there any reason for edk 9.1 registration failure with linux (I use the same id that successfully register...

1 19yrs

rponsard

1 19yrs rponsard

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