Field-Programmable Gate Arrays

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Beginner Advice (Languages, tools etc.)

Hi, Please excuse me for sounding like I don't have a clue what I'm talking about. I am here because I want to learn. I...
13 comments posted 19yrs
posted by rl
13 comments posted 19yrs posted by rl

add_file -verilog +define ..... filename.v

Hi, I have a question on Synplicity synthesis / FPGA synthesis. Is there a way to give in the `defines from the command...
0 comments posted 19yrs
posted by walke.abhijeet
0 comments posted 19yrs posted by walke.abhijeet

Spartan-3E Slave Serial Configuration

Hi All, I'm designing a circuit for configuring 4 Spartan-3E FPGA from an Atmel AVR microcontroller. I want to configur...
5 comments posted 19yrs
posted by ajg112
5 comments posted 19yrs posted by ajg112

Physical Design Contribution to FPGA/CPLD success

CPLDs and FPGAs both make (or made) use of "non-standard" implementation of digital circuits, namely wired-OR and pass-...
10 comments posted 19yrs
posted by acd4usenet
10 comments posted 19yrs posted by acd4usenet

Is post-place and route simulation useful?

Hi, Is the post place&route simulation so important? IMHO doing post synthesis (or post translate) simulation for verif...
6 comments posted 19yrs
posted by taileb.mehdi
6 comments posted 19yrs posted by taileb.mehdi

Open-Source VHDL Synthesis for FPSLIC?

Hi All, I've been doing some development work over the past year or so on the Atmel FPSLIC platform. I've run out of ti...
5 comments posted 19yrs
posted by jkrauss
5 comments posted 19yrs posted by jkrauss

Virtex-4 PCB design

Xilinx posts gerber file in *.pho format on their website for all of the evaluation boards. Does anyone no how to import...
1 comments posted 19yrs
posted by cstring625
1 comments posted 19yrs posted by cstring625

MicroBlaze Tutorial

Can anyone suggest a tutorial for MicroBlaze? I have googled it and found many tutorials, however, most seem to emphasi...
3 comments posted 19yrs
posted by bradsmallridge
3 comments posted 19yrs posted by bradsmallridge

Problem with Microblaze max clocking

Hi everybody, I'm using EDK 9.1i and in my design I use a Microblaze core (v 6.00.b). The device is a xc2v1000-4 (in a...
2 comments posted 19yrs
posted by cispa
2 comments posted 19yrs posted by cispa

Virtex5 PLL for DDR2 interface

I used the ISE 9.2 MIG to create a DDR2 mem controller for 267MHz memory chips, and it included a DCM to generate the 2...
1 comments posted 19yrs
posted by barry374
1 comments posted 19yrs posted by barry374

Peripheral Trouble!

Hello, I am using the xilinx virtex II development board xupv2p. I have built a expansion board that connects to the hi...
3 comments posted 19yrs
posted by mjp500
3 comments posted 19yrs posted by mjp500