Field-Programmable Gate Arrays

Walking 1's

Could some one please let me know what does Walking 1's means and what is it used for? Thanks in advance, Walters

3 comments posted 18yrs

posted by hpsham

3 comments posted 18yrs posted by hpsham

www.fpga-games.com website died?

looks like the website is down, any info if it that is temporary or not? Antti

2 comments posted 18yrs

posted by Antti.Lukats

2 comments posted 18yrs posted by Antti.Lukats

please help me for vhdl code of temprature controller

hi i have information about the vhdl code for room temprature controller at nanaware snipped-for-privacy@rediffmail.com

1 comments posted 18yrs

posted by nanaware_amit

1 comments posted 18yrs posted by nanaware_amit

XUPV2P from digilentinc

Is it possible for a hobbiest to obtain the board for USD 300? Any downside getting this board? Regards, John

13 comments posted 18yrs

posted by johnzulu[at]yahoo.com

13 comments posted 18yrs posted by johnzulu[at]yahoo.com

[offtopic] job inquiry; entry/trainee FPGA/ASIC designer

Hi! It seems that many subscribers of this group are professional FPGA/ ASIC designers working for European companies....

5 comments posted 18yrs

posted by theanonymous83

5 comments posted 18yrs posted by theanonymous83

Programming the ARM7 used to download our Xilinx FPGA

Ok, this doesn't have much to do with fpga's, but I need some help and you guys are a great knowledge base. In all our...

4 comments posted 18yrs

posted by danielgkNOSPAM

4 comments posted 18yrs posted by danielgkNOSPAM

2 leg crystal on FPGA: Lattice vs Xilinx

Hi I know many wise men has said NO NO, but 1) http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&threadi...

29 comments posted 18yrs

posted by Antti.Lukats

29 comments posted 18yrs posted by Antti.Lukats

LVDS clock management

Hi, I need a 1:8 (ok 1:10 is good too) differential LVDS clock driver with clock bank enable (individual clk enabling o...

1 comments posted 18yrs

posted by piclist9

1 comments posted 18yrs posted by piclist9

FPGA NTSC signal with 2 resistors and PWM

Hi I am evaluating the possibility to use 2 resitor video output from FPGA similar to: http://www.excamera.com/articles...

18 comments posted 18yrs

posted by Antti.Lukats

18 comments posted 18yrs posted by Antti.Lukats

PowerPC Simulation

I am simulating the PowerPC and can't find the damn program counter. I have looked in the reference manuals that come w...

2 comments posted 18yrs

posted by mottoblatto

2 comments posted 18yrs posted by mottoblatto

Xilinx upgrade

please i=B4m very new on this, whats the difference between Xilinx ISE and Xilinx=B4s EDK, and what for is the IP ???

4 comments posted 18yrs

posted by emrith

4 comments posted 18yrs posted by emrith

UCF Constraints: drive and slew

Hi, I need some help in this design: I use a design in which I have detected some skew problems. I have seen the archiv...

2 comments posted 18yrs

posted by pbantunez

2 comments posted 18yrs posted by pbantunez

FPDP to PCIe

Hi Everyone, Are there any hardware modules that I can buy to convert a data stream (serial FPDP over fibre) into PCI e...

1 comments posted 18yrs

posted by jayasanka.piyaratna

1 comments posted 18yrs posted by jayasanka.piyaratna

Bug in Synplify?

Hi, I have a behavior in Synplify Pro for Actel Fpgas I would call a bug (seen in each old version I could find up to t...

11 comments posted 18yrs

posted by usenet_10

11 comments posted 18yrs posted by usenet_10

Basic questions about the Nios II.

Hello. I'm getting a better outline of what's available and the differences between the different options, such as FPGA...

9 comments posted 18yrs

posted by NickHolby

9 comments posted 18yrs posted by NickHolby