Quartus-II 7.2 has improved upon Quartus's Systemverilog preprocessor:
`define SET_REG( x, y ) reg_``y
Quartus-II 7.2 web-edition Systemverilog improvements
Oct 10, 2007
1 Replies
Greatest. SystemVerilog looks much attractive than conventional VHDL \Verilog and even SystemC. There is only one reason why I haven't started yet synthesable altera project in SV: I wasn't sure about claimed support SV by the Quartus.
Tell us please, have you got already successful completed at least one altera's SV project?
Digitally yours, Michael Tsvetkov
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