HELP, how to time constraint part of a design?

Timing constraints vary by tool, what are you using?

If you are using Xilinx/ISE and you are using a DCM to divide your 80 MHz clock down to 40 MHz, timing constraints you put on the 80 MHz clock will be propagated through the DCM and adjusted accordingly.

Regards,

John McCaskill

I'm using Xilinx ISE WebPack for my design. I have 4 ADC interface entities that operaates on a 80MHz clk that I'm creating from an external 20MHz clock with a DCM. The calculation part (having a MAC-operation) must run on a

40MHz clock (divided from the 80MHz clock).

I mean I would like to make a local time constraint for an entity (if that makes things more clear). :-)

Are you going to have a separate clock domain clocked at 40MHz? Then you put a 25nS period constraint on the entire domain, not an entity. The same kind of constraint as on your 80MHz clock. But how are you handling getting data across the domain boundaries? That can be tricky.

Or are you going to clock everything at 80MHz, but have an enable in your "calculation part" that toggles, effectively operating it at 40MHz? This would be a better idea. You would apply a multicycle constraint, but that also can be a tricky thing to get right.

But the best thing to do would be to figure out why your MAC cannot operate at 80MHz, and fix it. How you do that depends somewhat on what device you are using. Are you using a device with builtin hardware multipliers? Then the first step would be to look in the project.syr file, and look for the word "pipeline". Look down through that section and see if there is something like: INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult__mult0004 by adding 1 register level(s). If so, you probably just need to pipeline your multipliers more. Make sure to go through the file and find all instances of the word "pipeline".

When the ADC-interface has a sample ready it signals this by setting a signal high for two 80MHz clk cycles. The calculator enity operates at 40MHz from the divided 80MHz clock. The clock division is simply made vith a t flip-flop in an entity.

The ADC-interface entity must be clocked at 80MHz to be able to sample at a specific rate. And the calculations (an IIR filter from an older design) only rund at max 50MHz (so i want to run it stable at 40MHz). So i would like to make sure that it meets that timing constraint.

I like to design with a top schematic where I connect all sub entities. Is there a way to insert the timing constraints in the schematic?

After it goes through the flip flop, it had better go through a global clock buffer, or your circuit is almost gauranteed not to work.

You seem to think attaching a timing constraint to the 40MHz piece will magically make your circuit work right. But it sounds like you have data crossing between the 80MHz domain and the 40MHz domain. If you simply allow the data to cross between them, it is likely your circuit will be flaky at best. So again, I will repeat. How are you handling getting data across the domain boundaries?

I think you really do want to fix your IIR to run at 80MHz; that will insure your circuit works right the first time, and every time.

Oh, and why are you using schematics ;)

There may be other issues with you design, but to solve your immediate problem you can declare the 40MHz clock a separate clock/timing group.

Yes, that is what I said in my first post in this thread ;)

Sorry! I missed that.

Hello, I'm very interested into this topic as I am tryin to implement a feedback loop (PID controller) with a spartan3e starter kit with xilinx ISE. The + and * operation is taking almost 40ns which is much more than 20ns limit for 50MHz operation. So I cut the operation is 3 sub operations so it fits into 19.98ns. I'm not sure it is the right way to do it but it seems to work. But still I get the message "INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_sig_d_00_mult0001 by adding 2 register level(s)." for the operation "sig_p

Thank you Brian for your reply. Unfortunately, I'm far from being a specialist and I'm not sure I quite understood everything

Indeed, for now it's ok, but I had to cut the formula into pieces with a counter to be able to meet timing requirement. The price to pay is that the formula is no more computed into 1 clock cycle but into 2 or more cycles with an added counter.

The reason why I forst wondered about this problem is because at first the loop worked sometimes and would have weird behaviour when changing almost insignificant parts of the code. For example, some integer comparisions were wrong. I then realized that even if the ISE "place and rout report" said that the 50MHz timing constraint "TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%" was always met, the ISE "Synthesis report" would say "maximum frequecy: 20MHz" but without issuing any error (do they check different things?). Then I cut the formula into pieces until I had both report agreeing on the maximum frequency and the problem was solved, with added complexity.

What does "add more pipeline registers" mean? does it mean cutting even more into pieces? Then I still have the "number of cycles price" to pay?

I don't for now but might want it to run faster in another setup.

By the way, the limit with this setup is linked to the serial interface of the ADC/DAC, preventing me from getting above frequecies around 20kHz. Do you know another cheap kit with several ADC/DAC with "parralel access" or do I have to take a standard dev. kit and add a custom AD/DA daughter card

Thanks in advance for your reply! laurent

This sounds like adding pipeline stages.

The ISE synthesis report gives an estimate of the maximum frequency, a prediction of what PAR might do, but not an accurate figure. I have often found it 10% or more out. But never as far off as 20MHz instead of

50 MHz... If it's that far off you were correct that you had to fix your code.

The PAR report contains the accurate figure, and the .twr trace report contains more detail about which paths were too slow.

It does increase the number of cycles latency, but you can start a new computation each cycle, so throughput is high. Of course, for a control loop, latency is probably important; that's why you need to simulate to check stability if you add latency.

and may be of interest

- Brian