Unrouted nets (Xilinx FPGA Editor)

Hi all,

I meet some problems in the P&R process of my design.

The Place & Route Report shows the following messages. Because it stoped at Phase 6 for a long time, I paused it and it shows there's 1 net unrouted.

----------------- Place & Route Report ------------------------ Phase 6: 2645 unrouted; (0) REAL time: 17 secs

Ctrl-C interrupt detected.

Please choose one of the following options: 1. Ignore interrupt and continue processing. 2. Exit program normally at next checkpoint. This will save the best results so far after concluding the current processing. 3. Exit program immediately. 4. Cancel the current job and move to the next one at the next check point.

Enter choice --> 2 User requested termination Phase 7: 1 unrouted; (0) REAL time: 3 mins 2 secs


I opened the ncd file and shows the Unrouted Nets visually. I changed the position of one of the SLICE and then it automatically re-route. The previously Unrouted Nets dissapered and are no longer listed.

But I'm not completely sure that all of the nets have been routed properly, because in the following step, Generated Programming File, it complains that ERROR:PhysDesignRules:801 - The network has routing conflicts. ERROR:PhysDesignRules:801 - The network has routing conflicts. ERROR:Bitgen:25 - DRC detected 2 errors and 24 warnings.

I checked the ncd file again in the FPGA Editor, however, it seems these two nets have already been routed. what is "the routing conflicts" meant to? Any possible solutions?

I would appreciated your help, Ju, Jian

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Ju, Jian
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maybe what you need to do is run generate program file again

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Another try, let open a working design in FPGA editor, unroute something and save it off, then try to generate the program file. If you are able to do so, that means you're still generate bit file from the old net...just a though,

I do see couple of "failed routing" like that..., just simply re-run all and it works again. If the problem consistent, call Xilinx and "pray"

good luck

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