Field-Programmable Gate Arrays

Is it possible to check how cache memories are mapped to FPGA block rams?

Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems that the cache memories of the processor are not b...

7 comments posted 18yrs

posted by camwwang

7 comments posted 18yrs posted by camwwang

2 FPGAs /w programming FLASH in one JTAG chain

Hi there, currently I am designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. It should be possible to program...

6 comments posted 18yrs

posted by mistertorpedo

6 comments posted 18yrs posted by mistertorpedo

How to make sure processor memories have been correctly mapped onto block ram on fpga?

Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems that the cache memories of the processor are not b...

0 comments posted 18yrs

posted by camwwang

0 comments posted 18yrs posted by camwwang

FPGA Configuration

Hello VLSI Engineers. Its is true that FPGA boots its program from an external PROM. How external eproms are connected t...

11 comments posted 18yrs

posted by clickonjaseel

11 comments posted 18yrs posted by clickonjaseel

Final CFP: 2008 International Workshop on Multi-Core Computing Systems

*********************************************************************** EXTENDED PAPER SUBMISSION DEADLINE: November 20...

0 comments posted 18yrs

posted by Sabri.Pllana

0 comments posted 18yrs posted by Sabri.Pllana

Xilinx xflow for the ISE Quickstart Tutorial project?

Hi I've gone through the ISE Quick Start Tutorial and can get its 4 bit counter downloaded and working on a Digilent bo...

3 comments posted 18yrs

posted by usenet

3 comments posted 18yrs posted by usenet

HPCNCS-08 Call for papers

The 2008 International Conference on High Performance Computing, Networking and Communication Systems (HPCNCS-08) (webs...

0 comments posted 18yrs

posted by jeedward

0 comments posted 18yrs posted by jeedward

total equivalent gate count

Hello all, The ISE map report gives out a figure under the heading total equivalent gate count... So can anybody help m...

1 comments posted 18yrs

posted by nagarajputti

1 comments posted 18yrs posted by nagarajputti

Selecting I/O pins

Hi, I was recently asked in an interview that what points you will consider while selecting the I/O pins in FPGA ? One...

2 comments posted 18yrs

posted by vedpsingh

2 comments posted 18yrs posted by vedpsingh

Bitfile checking

Assuming a scenario that I have a bit file built for a particular FPGA, but i don't have a that FPGA device to download...

6 comments posted 18yrs

posted by hpsham

6 comments posted 18yrs posted by hpsham

How to use an internal signal in a testbench...

I am simulating an EDK system and want to use some internal signals at the testbench level (without routing them up to...

3 comments posted 18yrs

posted by mottoblatto

3 comments posted 18yrs posted by mottoblatto

Re: Xilinx Isolate circuitry

> Hi all, > > In our design, we have a sensitive circuitry that we think may be affected > by the bulk of the circuit (...

3 comments posted 18yrs

posted by davidmspencer

3 comments posted 18yrs posted by davidmspencer

XMD with CableServer OR remote EDK solution

Hi, Is it possible to run XMD remotely using CableServer? This is the only missing item that would enable me to work co...

4 comments posted 18yrs

posted by prdubois

4 comments posted 18yrs posted by prdubois

FPGA vs ASIC

When it comes to designing for fpgas or asics there are a lot of guidelines/rules that need to be followed consistently...

32 comments posted 18yrs

posted by fpgabuilder-groups

32 comments posted 18yrs posted by fpgabuilder-groups

"SPI indirect" programming for any FPGA/CPLD

Hi attached to xilinx forum message http://forums.xilinx.com/xlnx/board/message?board.id=OTHERIP&thread.id=19 is a simp...

0 comments posted 18yrs

posted by Antti.Lukats

0 comments posted 18yrs posted by Antti.Lukats