Is it possible to check how cache memories are mapped to FPGA block rams?

depends on the definition of "correct" you can use FPGA editor to see the mapping to device primitives if you wish but that want tell you why your design is not working

Antti

Perhaps if you post the actual project (or put a copy on a web site and post a URL), some of us can take a look at it and try to help debug it. Otherwise we don't have very much to go on.

Eric

Eric, I appreciate your willingness to dig further to help, but my question was how I could check the block ram mapping of my design which I thought it was quite generic, and I would expect answers, such as, look at somewhere or look for something in the synthesis log file, or open fpga editor and look for instantiations of primitives. BTW, I suppose most of us in this group do not work for ourselves, only lazy university students would post their entire project and let somebody else do the work for them. Thanks!

Now, now. Don't be too hasty. That's what we do with Xilinx all the time when their software tools don't work "just right" or you hit that invisible brick wall that only someone with eyes from inside the brick wall can tell you why the wall exists (read: Webcases).

So long as what you're working on is not proprietary, the nature of "open source" mindedness is to share with others and gather feedback. That's what posting your MHS file would provide.

I am not sure that putting his expensive ARM1176 core on the web would be appreciated by ARM :-)

Did you write this core yourself? if not then I am sure you can get some excellent support from ARM to fix this issue,

Hans

Without looking at your HDL code, I don't think we have any clue how you've attached the blockrams to your CPU, so I'm not sure how we could tell you how to check the mapping.

In general, I agree. But sometimes it's hard to offer any help without more detail, and sometimes the easiest way to see the relevant detail is to look at the HDL.

I'm sorry that I don't have any more specific advice to offer.

Best regards, Eric

Wei,

I have worked with an ARM926 soft core. This deliverable provided an implementation guide as well as a simulation environment to verify the RAM integration. I would have thought the ARM11 would have a similar thing.

Whether it is FPGA or ASIC the RAM integration follows the same process. The RTL simulation environment will ensure you have correctly connected the memories.

Mike