total equivalent gate count

Hello all,

The ISE map report gives out a figure under the heading total equivalent gate count... So can anybody help me in understanding what exactly it means?How can we relate it to the ASIC gate count of the same design?

Regards, Nagaraj

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I would use it as a relative indication.

At one time, "gate count" referred to the number of 2-input NAND or NOR functions required. This was (roughly) an ASIC-like measure of complexity.

However, FPGA devices have ways of implementing a function which do not "convert" well to ASIC gates, hence, I would not use the "gate count" to estimate what an equivalent ASIC would take, but rather to estimate how to compare one design in the same FPGA arhitecture with another.

If you wish to check for ASIC gates, I would synthesize the same VHDL, or verilog, with an ASIC standard cell library in order to find how many "gates" an ASIC version of the same design would really take.


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