How to use an internal signal in a testbench...

Your design and testbench are all in Verilog, right?

Apart from the missing semicolon at the end of the wire assignment, this is perfectly valid Verilog; so I suspect ModelSim is right, and you have made some small error in the hierarchical name. Case sensitivity?

Yeah. The string is a very wide Verilog constant; because its last character is '0', whose ASCII code is an even number, your single-bit wire will be jammed to zero.

The leading '.' would be wrong in any case.

Same reason: you've assigned a 34-character string, which is an 8*34-bit constant vector, to the wire. Its LSB happens to be zero, so that's what you get.

The slashes would never work in a Verilog hierarchical name.

That all sounds correct. Sanity check: this is *really* all in Verilog, right? Every level of the hierarchy? And that hierarchical path really is starting from the very top of your hierarchy?

Here's another thought: Can you, temporarily, patch the code of the lowest level of the hierarchy - the place where "clk0" lives? If so, put this code right next to the declaration of "clk0" (or, if it's a port, somewhere inside the module that has it as a port):

initial $display(" The signal I want is at %m ");

The %m formatter will display the full Verilog hierarchy path to that point in the design. Add ".clk0" to the end of that name, and that's your signal name.

If all else fails, look at the ModelSim docs for "SignalSpy".

Thanks Jonathan,

The project is NOT all in Verilog. The EDK uses VHDL wrappers for all the modules and I am using Xilinx IP cores which are written in VHDL. The testbench and the system are in Verilog. Underneath that level are all VHDL wrappers. Some modules inside the wrappers are Verilog and some are VHDL. I have pointed ModelSim to the unisims_ver library which contains the Xilinx primitves in Verilog. I am pretty sure the DCM model would be used from here so it should be Verilog, but again, its wrapper is in VHDL.

Is there some trick when you traverse hierarchy of diferent languages?

I did try to use signal spy, but it didn't work either. It produced either a static 0 signal or a static z signal, but I may revisit that to see if I was doing things incorrectly...which is quite possible!

I think that's the problem; I don't believe you can read "through" a VHDL wrapper, not even into a Verilog lower-level module. But I could be wrong - it's a while since I played with that sort of thing in ModelSim.

Probably, but it might be worth asking your Mentor AE or distributor...

Again, I don't know enough about SignalSpy to be sure what happens in a mixed-language environment, but I *thought* it could see anything the simulator can see. Probably a case of RTFM carefully (again). Good luck.