Hi, I was recently asked in an interview that what points you will consider while selecting the I/O pins in FPGA ?
One thing which came to my mind was :
1) considering board aspect that the pins corresponding to peripherals should near to that peripheral so as to minimize the routing delay in PCB.2) pin should be compatible to the I/O type of peripheral device, i.e. LV_TTL, LC_CMOS etc.
Were my points valid ? Any other points are welcome.
Regards
Hi -
[3] Some I/O pins are - Input Only - Lack IOB FFs - Dedicated clk input - For DRAM interfacing there may be specific pins reserved for specific signals [4] In some families (Spartan 3/3E), only 2.5 V Differential signaling supported, not 3.3 V. The important corallarys are : Banks which contain dfferential signaling must have VCO tied to 2.5, and this precludes single ended 3.3V signals from being used in that bank.Sometimes the subtleties of IO are overwelming, and vary slightly from family to family. One thing I try to do before a pwb is sent out for the first time, is to code the I/O for the final pin selection, and synthesize. This is pretty easy, will be the first thing done when coding anyway, AND allows you to view the generated report files for any possible bad. or more likely, non-optimal pin assignments.
There is a section in the .mrp file and in the .pad file which should be reviewed to ensure what you want is what you got.
-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado Based Xilinx Consultant email : jretta@rtc-inc.com web : www.rtc-inc.com "Ved" wrote in message news:1193488229.776279.239100@e34g2000pro.googlegroups.com... > Hi, > I was recently asked in an interview that what points you will > consider while selecting the I/O pins in FPGA ? > > One thing which came to my mind was : > 1) considering board aspect that the pins corresponding to peripherals > should near to that peripheral so as to minimize the routing delay > in PCB. > > 2) pin should be compatible to the I/O type of peripheral device, i.e. > LV_TTL, LC_CMOS etc. > > Were my points valid ? > Any other points are welcome. > > Regards >
I would have mentioned something about in an ideal world making sure you can achieve timing closure before committing to a PCB. These days, the effect of I/O location on design performance is much, much less significant than it was, say, ten years ago - largely because of better and faster on-chip routing, but if you are pushing the limits then the I/O selection can make all the difference.
Of course, since it was an interview question, the "right" answer would probably some talked about working as a team with the PCB layout people and choosing a pin-out that is acceptable to both groups.
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