2 FPGAs /w programming FLASH in one JTAG chain

The two proms can be considered as one big prom twice as large. No prom is exclusively dedicated to one FPGA in particular. For example, the bit file for FPGA #1 might take 2/3 of the first prom and the bit file for FPGA #2 might be half in prom #1 and half in prom #2. This is handled for you when you create your mcs files for the proms.

For the hardware connections, refer to the platform flash guide, page

Patrick

components should be part of one coherent JTAG chain.

Argh: a crosspost to many groups!

What's wrong with Figure 8 of the DS123 datasheet?

Since you want one Flash per FPGA, you just connect the Flashes to the FPGAs as if there was only one of each. You can then connect the JTAG chain through all four devices in whatever order you want.

"Patrick Dubois" schrieb im Newsbeitrag news: snipped-for-privacy@k35g2000prh.googlegroups.com...

Okay, thank you very much. But one more question: What about the DO pins from the PROMs to the FPGA? In the Platform Flash In-System Programmable Configuration PROMs data sheet ds123.pdf (page 18) it is recommended to tie the DO outputs of both PROMs together and connect the FPGAs in series. I don't see any reason to do it this way. What I would have done normally (without having read the user guide) is having the DO of one PROM connected to one FPGA (DIN) and the other DO of the second PROM to the the other DIN of the remaining FPGA. What is the reason not to do so, i.e. is there any reason? Any help is highly appreciated!

Regards

Toni

Newsbeitragnews: snipped-for-privacy@k35g2000prh.googlegroups.com...

Surely this is a simple bom cost option. If each fpga needs 4.1 Mbit you would need two 8MBit PROMs seperately or an 8 and a 1MBit if combining them.

"colin" schrieb im Newsbeitrag news: snipped-for-privacy@22g2000hsm.googlegroups.com...

So I'm fine with my solution if cost doesn't matter, right? :-) Technically it is not wrong, I guess...