Xilinx xflow for the ISE Quickstart Tutorial project?

Here is a .bat file I use to build from Verilog source to a .bit file. I invoke by typing : make_xst_FPGA_NAME.bat FPGA_NAME 01

The first command line parameter is the root name for fpga ... For instance, the .ucf file would be named with this prefix, all the resultant files named with this prefix, etc.

Second command line is the rev level for the build. Note that I use this in the bitgen command line to specify the user ID. This is helpful in that when a rogue board shows up, the current revision can be determined via reading this parameter with the JTAG programming pod.

cd .. rmdir /s /q synth mkdir synth cd synth

xst -ifn ..\scripts\xst.txt -intstyle xflow

ngdbuild -p xc3s250e-4-vq100 -uc ..\files\%1.ucf %1

map -k 6 -detail -pr b %1 rem pause

par -ol med -w %1.ncd %1_r%2

copy %1.pcf %1_r%2.pcf

trce -e -o %1_err.twr %1_r%2 trce -v -o %1_ver.twr %1_r%2

rem ************************************************** rem * first make bitgen for rom, then remake for JTAG rem ************************************************** rem bitgen -w -g UserID:555500%2 %1_r%2 %1_r%2 bitgen -w -g UserID:55550%2 -g DonePipe:yes -g UnusedPin:Pullup %1_r%2 %1_r%2

-------------------------------------------------------------------

The contents of xst.txt is :

run

-ifn ..\code\flist_FPGA_NAME.v

-ifmt Verilog

-ofn FPGA_NAME.ngc

-ofmt NGC

-p xc3s100e-4-vq100

-opt_mode Speed

-opt_level 1

-top FPGA_NAME

-------------------------------------------------------------------

The contents of flist_FPGA_NAME is :

`include "..\code\FPGA_NAME.v" `include "..\code\FPGA_NAME_SUB_MOD1.v" `include "..\code\FPGA_NAME_SUB_MOD2.v"

-------------------------------------------------------------------

Lastly ... yes .. this is a DOS batch file. But the point is it can easily be ported to a script for whichever OS you are currently using.

... One more thing. Under Xilinx/Doc/usenglish/book/docs/ are various subdirectories with .pdf files.

Check the /dev for the developers reference guide, /lib for the library guide, /xst for info on xst.

Regards, John Retta Owner and Designer Retta Technical Consulting Inc.

Colorado Based Xilinx Consultant

email : snipped-for-privacy@rtc-inc.com web :

Thanks, John. I had found your .bat file with google but was a little intimidated by all the references. I shouldn't have been -- it wasn't really that difficult. Without worrying about Makefiles or scripts, here is the list of command required to build and install the counter to the board for rev# 123.....

xst -ifn xst.txt -intstyle xflow ngdbuild -p xc3s200-4ft256 -uc counter.ucf counter map -k 6 -detail -pr b counter par -ol med -w counter.ncd counter_r123 cp counter.pcf counter_r123.pcf trce -e -o counter_err.twr counter_r123 trce -v -o counter_ver.twr counter_r123 bitgen -w -g UserID:55550123 -g DonePipe:yes -g UnusedPin:Pullup counter_r123 counter_r123 impact -batch impact.bat

I used your xst.txt file modified for the FPGA on the Digilent board. The commands loaded into "impact.bat" I got by running the download tool in ISE and grepping out "BATCH CMD" from the log file. I consider this the "hello world" of FPGA so now I can go back and figure out what each command is doing.

One final question, what command would make a prom image (.mcs) for this?

thanks Bob Smith

Hi Bob - After bitgen, promgen -w -s 512 512 -p mcs -u 0 %1_r%2

There are lots of reasons to use a script approach. The biggest are that your synthesis is now easily portable (give someone the source, the synth script, and the same ise revision of tools, and the bitfile that is generated will diff. Of course this is possible in the gui flow ... just an order of magnitude more difficult.

Other point is that the whole synthesis flow is defined with a few small ascii files. Easy for configuration control.

Good luck.