Hi FPGA Group!
I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM interface, generated with the Xilinx Memory Interface Generator. The complete system consists of a PCI interface, an I/O DMA buffer, a burst module bursting from DMA buffer to the DDR2 DRAM interface.
What is the best way to define setup/hold times for the I/O pads (UCF)? (the RAM interface consists of a bi-dir data bus DQ, some output signals e.g. A and the DRAM clocks CK)
- Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this does only work using the Input Clock Pin, but it should probably better be in reference to the DRAM clocks CK)
- Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is probably better, but I'm not exactly sure.
Furthermore, how would you tackle the problem if the timing at the pads cannot be met?
Thanks in advance for helpful answers and pointers in the right direction!
Best regards, Simon