Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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APU (xilinx PPC) is it a soft core ?
Hi all, I have a simple question - is the APU controller is part of the FPGA/ PPC silicon or is it a soft-core that is added only when used ? Thanks, Mordehay.
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16 years ago
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Xilinx PCI-express coregen
There are some MAXDELAY=1ns constrain for TX signals inside PCIE coregen. eg: (* MAXDELAY="1.0" *) wire [1:0] tile0_txcharisk0_r; (* MAXDELAY="1.0" *) wire tile0_txdetectrx0_r; (* MAXDELAY="1.0" *)...
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16 years ago
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Xilinx PCI-Express Endpoint Block IP
There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it needs 250MHz general,it is impossible to achieve 250Mhz clk with large need 16bit...
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16 years ago
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Static PLL
Hi all, I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 evaluation board, I try to use the Static PLL macro from the Libero IDE since in the documentation of ACTEL they tell us to use...
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16 years ago
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Problem using xilinx usb download cable in linux
Hi all, I have spent quite some time on the net trying to find info on how to get the xilinx usb download cable to work with linux and I have reached a dead end. :( I have installed the usb-driver...
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16 years ago
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How do I meet this memory IO with least resources on FPGA?
Hi, there My design needs a 16X16 matrix, each of 32-bit. The matrix must be read row by row or column by column each in one clock.. Direct register implementation takes a lot of resources and routing...
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16 years ago
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Synthesizing with specific primitive-elements
Hello, I want to synthesize my VHDL code targeting an ASIC design, and I want to do this using as primitive elements only NAND gates and d-flip- flops. So, basically what I think I have to do is...
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16 years ago
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Spartan-3 (XC3S400) DDR LVDS support?
What Mbps speed does DDR LVDS serializer in XC3S400 transmission support? (for use with TFT screens or backplane)
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16 years ago
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Xilinx EDK and Windows Vista?
I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit only), but it requires Xilinx ISE 9.1i, which isn't compatible with Vista at all. Is there a timetable for EDK support or...
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16 years ago
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code hang after loading through gdb
Hi, I'm trying to do a design with dual ppc on an ml410 board with virtex 4. I first followed an example given on xilinx website and everything seems to be ok. But after I add only one more uartlite...
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16 years ago
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To Xilinx users - PLB bus features (for PPC)
Hi, It is mentioned in xilinx data sheets that the the CoreConnect PLB bus has lots of great capabilities (e.g. address pipelineing , bursts etc.). I wonder how can I (as a user) can bring the PPC to...
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16 years ago
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Xilinx's System Generator versus Mathworks' Link for Modelsim
I am mainly looking to make my ModelSim test bench simulation creations easier/faster. How does Xilinx's System Generator versus Mathworks' Link for Modelsim compare for that? With System Generator, I...
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16 years ago
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fpga based designs
Dear all, Is it possible to implement power management unit(idle and active) in FPGA? pls give suggestions to implement clock generation unit in FPGA.... regards, fazal
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16 years ago
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Another way to handle floating inputs.
Has anyone implemented a circuit similar to the one below? VCC + | .---------------o | | | | | .-. | | | | | | weak pullup | '-' | | | | | .-----o | | | ----- | || | | | --------| >-----|-------| PIN...
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16 years ago
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ISE ignores LOC constraints for BUFGMUX clock buffers
Hi all! I have a simple Spartan3A design where I feed a digital video stream to bank 3 of the device. The idea is to use one of the Left hand clocks in the device to clock data in the IO pads and to...
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16 years ago
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