Field-Programmable Gate Arrays

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FPGA Clock signal

i would like to ask how can i capture the FPGA master clock signal in the oscilloscope? Bcos in the data sheet, it indi...
5 comments posted 18yrs
posted by raullim7
5 comments posted 18yrs posted by raullim7

Time Delay in FPGA

hi, i have two processes in my vhdl code for my FPGA. the two processes each will generate a signal with the second one...
1 comments posted 18yrs
posted by raullim7
1 comments posted 18yrs posted by raullim7

ERROR:MDT - transparent bus interface connector

Hello all, I am facing the error below when i am doing generate libs and BSB's. ERROR:MDT - transparent bus interface c...
2 comments posted 18yrs
posted by lastval
2 comments posted 18yrs posted by lastval

May i program a Spartan 3 fpga with a 1,8 V Digilent cable?

Hi ,i like to use cpld and fpgas scraped by boards at home at the purpose of practicing VHDL. I have some Spartan 3 XC3...
2 comments posted 18yrs
posted by bliscachiocciolinatiscali.it
2 comments posted 18yrs posted by bliscachiocciolinatiscali.it

not totally repulsive

I usually have +5 volts available in VME modules, so I generally linear-regulate down from +5 to 3.3, 2.5, and 1.2 for...
36 comments posted 18yrs
posted by jjlarkin
36 comments posted 18yrs posted by jjlarkin

Linux capable free/GPL SOFT CPU for XC3S500E?

Hi All, I'm looking for a possibility to run Linux (may be a ucLinux) on a XC3S500E containing CPU and some custom peri...
11 comments posted 18yrs
posted by wzab
11 comments posted 18yrs posted by wzab

FPGA I/O Selection in UCF

I have an application with a Xilinx Spartan3 FPGA where I would like to use a single FPGA binary to support to I/O volt...
7 comments posted 18yrs
posted by jtindle
7 comments posted 18yrs posted by jtindle

linking error using mb-g++

Specification EDK version:8.2i FPGA Board: Virtex II Pro My source code requires g++ compiler. However, when trying to...
0 comments posted 18yrs
posted by priyanthads
0 comments posted 18yrs posted by priyanthads

Global Variables

i am having two PROCESS to take advantage of dual-edge behavior of the clock pulse. one process takes care of the risin...
2 comments posted 18yrs
posted by raullim7
2 comments posted 18yrs posted by raullim7

Linux (not uClinux) on Microblaze 7.0 w/MMU?

Now that Xilinx has released Microblaze 7.0 with an optional MMU (in EDK 9.2), has anyone started working on a Linux po...
2 comments posted 18yrs
posted by eric
2 comments posted 18yrs posted by eric

Audio Output from Spartan 3 Starter Kit

Hello, I would like to try to get some audio output from my Spartan 3 starter kit board, but as a hardware novice I wor...
4 comments posted 18yrs
posted by hansen.bryan
4 comments posted 18yrs posted by hansen.bryan

DDR2 Interface

Hi I am designing a board with a Virex 4 and a DDR2 component. I have use the MIG tool to generate an interface. Howeve...
1 comments posted 18yrs
posted by maxascent
1 comments posted 18yrs posted by maxascent

APU (xilinx PPC) is it a soft core ?

Hi all, I have a simple question - is the APU controller is part of the FPGA/ PPC silicon or is it a soft-core that is a...
1 comments posted 18yrs
posted by me_2003
1 comments posted 18yrs posted by me_2003

Xilinx PCI-express coregen

There are some MAXDELAY=1ns constrain for TX signals inside PCIE coregen. eg: (* MAXDELAY="1.0" *) wire [1:0] tile0_txc...
1 comments posted 18yrs
posted by water9580
1 comments posted 18yrs posted by water9580