Latest threads in Field-Programmable Gate Arrays

APU (xilinx PPC) is it a soft core ?

Hi all, I have a simple question - is the APU controller is part of the FPGA/ PPC silicon or is it a soft-core that is a...

1 19yrs

me_2003

1 19yrs me_2003

Xilinx PCI-express coregen

There are some MAXDELAY=1ns constrain for TX signals inside PCIE coregen. eg: (* MAXDELAY="1.0" *) wire [1:0] tile0_txc...

1 19yrs

water9580

1 19yrs water9580

Xilinx PCI-Express Endpoint Block IP

There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it ne...

2 19yrs

water9580

2 19yrs water9580

Static PLL

Hi all, I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 evaluation board, I try to use the Static PLL...

4 19yrs

claesvincent

4 19yrs claesvincent

Problem using xilinx usb download cable in linux

Hi all, I have spent quite some time on the net trying to find info on how to get the xilinx usb download cable to work...

5 19yrs

roger.jons

5 19yrs roger.jons

How do I meet this memory IO with least resources on FPGA?

Hi, there My design needs a 16X16 matrix, each of 32-bit. The matrix must be read row by row or column by column each i...

9 19yrs

G.Iveco

9 19yrs G.Iveco

Synthesizing with specific primitive-elements

Hello, I want to synthesize my VHDL code targeting an ASIC design, and I want to do this using as primitive elements on...

3 19yrs

giorgos.puiklis

3 19yrs giorgos.puiklis

Spartan-3 (XC3S400) DDR LVDS support?

What Mbps speed does DDR LVDS serializer in XC3S400 transmission support? (for use with TFT screens or backplane)

1 19yrs

kgll8ss

1 19yrs kgll8ss

Xilinx EDK and Windows Vista?

I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit only), but it requires Xilinx ISE 9.1i, which i...

4 19yrs

anonymous

4 19yrs anonymous

code hang after loading through gdb

Hi, I'm trying to do a design with dual ppc on an ml410 board with virtex 4. I first followed an example given on xilin...

3 19yrs

xmkong

3 19yrs xmkong

To Xilinx users - PLB bus features (for PPC)

Hi, It is mentioned in xilinx data sheets that the the CoreConnect PLB bus has lots of great capabilities (e.g. address...

1 19yrs

me_2003

1 19yrs me_2003

Xilinx's System Generator versus Mathworks' Link for Modelsim

I am mainly looking to make my ModelSim test bench simulation creations easier/faster. How does Xilinx's System Generat...

1 19yrs

brianwfarmer

1 19yrs brianwfarmer

fpga based designs

Dear all, Is it possible to implement power management unit(idle and active) in FPGA? pls give suggestions to implement...

4 19yrs

fazulu.vlsi

4 19yrs fazulu.vlsi

Another way to handle floating inputs.

Has anyone implemented a circuit similar to the one below? VCC + | .---------------o | | | | | .-. | | | | | | weak pul...

13 19yrs

Petrov_101

13 19yrs Petrov_101

ISE ignores LOC constraints for BUFGMUX clock buffers

Hi all! I have a simple Spartan3A design where I feed a digital video stream to bank 3 of the device. The idea is to us...

1 19yrs

noreply.larthe

1 19yrs noreply.larthe

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