Field-Programmable Gate Arrays

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Xilinx PCI-Express Endpoint Block IP

There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it ne...
2 comments posted 18yrs
posted by water9580
2 comments posted 18yrs posted by water9580

Static PLL

Hi all, I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 evaluation board, I try to use the Static PLL...
4 comments posted 18yrs
posted by claesvincent
4 comments posted 18yrs posted by claesvincent

Problem using xilinx usb download cable in linux

Hi all, I have spent quite some time on the net trying to find info on how to get the xilinx usb download cable to work...
5 comments posted 18yrs
posted by roger.jons
5 comments posted 18yrs posted by roger.jons

Synthesizing with specific primitive-elements

Hello, I want to synthesize my VHDL code targeting an ASIC design, and I want to do this using as primitive elements on...
3 comments posted 18yrs
posted by giorgos.puiklis
3 comments posted 18yrs posted by giorgos.puiklis

Spartan-3 (XC3S400) DDR LVDS support?

What Mbps speed does DDR LVDS serializer in XC3S400 transmission support? (for use with TFT screens or backplane)
1 comments posted 18yrs
posted by kgll8ss
1 comments posted 18yrs posted by kgll8ss

Xilinx EDK and Windows Vista?

I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit only), but it requires Xilinx ISE 9.1i, which i...
4 comments posted 18yrs
posted by anonymous
4 comments posted 18yrs posted by anonymous

code hang after loading through gdb

Hi, I'm trying to do a design with dual ppc on an ml410 board with virtex 4. I first followed an example given on xilin...
3 comments posted 18yrs
posted by xmkong
3 comments posted 18yrs posted by xmkong

To Xilinx users - PLB bus features (for PPC)

Hi, It is mentioned in xilinx data sheets that the the CoreConnect PLB bus has lots of great capabilities (e.g. address...
1 comments posted 18yrs
posted by me_2003
1 comments posted 18yrs posted by me_2003

fpga based designs

Dear all, Is it possible to implement power management unit(idle and active) in FPGA? pls give suggestions to implement...
4 comments posted 18yrs
posted by fazulu.vlsi
4 comments posted 18yrs posted by fazulu.vlsi

Another way to handle floating inputs.

Has anyone implemented a circuit similar to the one below? VCC + | .---------------o | | | | | .-. | | | | | | weak pul...
13 comments posted 18yrs
posted by Petrov_101
13 comments posted 18yrs posted by Petrov_101

ISE ignores LOC constraints for BUFGMUX clock buffers

Hi all! I have a simple Spartan3A design where I feed a digital video stream to bank 3 of the device. The idea is to us...
1 comments posted 18yrs
posted by noreply.larthe
1 comments posted 18yrs posted by noreply.larthe

can i use dual edge or two clocks?

My FPGA master clock is at 100MHz. I have assigned a counter to count from 0 to 99 to achieve a period of 1usec. As the...
15 comments posted 18yrs
posted by raullim7
15 comments posted 18yrs posted by raullim7

Digilent V2P Board

Using the Digilent XUP V2P Board, I have to use additional memory (256 Mb DDR SDRAM). The only memory drivers I can fin...
1 comments posted 18yrs
posted by td.binnie
1 comments posted 18yrs posted by td.binnie