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To Xilinx users - PLB bus features (for PPC)

Hi, It is mentioned in xilinx data sheets that the the CoreConnect PLB bus has lots of great capabilities (e.g. address pipelineing , bursts etc.). I wonder how can I (as a user) can bring the PPC to use these capabilities, saying how can I force a burst write or read ? or how can I start a write while a read is in progress ? Is there a special SW command/syntax that make the PPC PLB Date side master to write a burst or does it do it automatically ? I will be greatfull for any help on this.. Thanks, Mordeahy.

Reply to
me_2003
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The PowerPC will do single beat transactions (8 bit,16 bit, and 32 bit) and cache line transactions. If it is addressing memory that has been mapped as cacheable, it will automatically do a cache line transaction.The default is to do 32 byte cache lines, but you can set it to do two other sizes as well via one of the special machine state registers. I think that it is 16 and 64 bytes, but I would have to double check that. The PPC does not do any of the other burst transaction.

The data and instruction caches each have their own master PLB interface, so one of them can be doing a read while the other is doing a write. I do not believe that an individual PPC PLB interfaces will do simultaneous reads and writes, but I would have to look at the Xilinx PPC users guide to verify that.

The PLB bus will indeed support these modes. We have a PLB to DDR2 interface, and a PLB master interface that support simultaneous reads and writes for the single beat, burst and cache transactions, and it is a thing of beauty to watch that in action.

Regards,

John McCaskill

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slmccaskill

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