Another way to handle floating inputs.

Has anyone implemented a circuit similar to the one below?

VCC + | .---------------o | | | | | .-. | | | | | | weak pullup | '-' | | | | | .-----o | | | ----- | |\| | | | --------| >-----|-------| PIN | |/ | | | | ----- | | floating | or | GND /| | To Internal Fpga Logic

Reply to
Petrov_101
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Petrov,

Why are you trying to do this?

What is it supposed to protect the FPGA from?

Austin

Reply to
austin

Wow - How much noise is he used to dealing with ?

Also be worried about if the contention can get past the logic threshold.

Yes, "the fpga can handle it" - but you have wider issues. Can the device driving the fPGA handle it. You would need to spec the lowest drive option on the FPGA, and the best drive on the external device. What if the designer of the external device is thinking exactly the same as you :)

The 80C51 has a port structure similar, but they use Weak PFET and Strong NFET, so they know they will not get stuck in no-mans land with part variations.

-jg

Reply to
Jim Granville

I'm not convinced I should be trying this, that's the problem. I've always just enabled a weak pullup resistor on the input of a floating pin. My coworker is trying to convince me that this approach offers better noise immunity when nothing is connected to the input pin.

The thing is, this input feeds a two-stage synchronizer... I would think that alone would eliminate most noise to the synchronous logic that follows.

Reply to
Petrov_101

My coworker did suggest setting the drive to the lowest setting. I assume he's done this on past designs... I've just never seen it before.

Reply to
Petrov_101

Similar structures can be used for contact de-bouncing. Use a single-pole double-throw switch, connect the two poles to Vcc and ground, and the moving arm to the FPGA input/output. When input senses a Low, make the output drive low. When the input senses High, make the output drive High. The switch easily overrides the output driver (make it weak), and the current spike lasts only a few nanoseconds. Doesn't work with a single- throw switch... Peter Alfke

Reply to
Peter Alfke

This looks like "voodoo design" to me. See

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for the software equivalent.

If you know what the problem really is, design for that. Use series o parallel termination to mitigate ground-bounce, for instance.

Reply to
RCIngham

Reply to
Peter Alfke

Why not use a weak keeper instead? Older Xilinx part used that internally on tristate lines. You have a weak buffer that drives the line to the voltage seen on the line. An undriven line will quickly be driven to either 1 or 0 due to initial noise. Another circuit driving the line will need to overcome the keeper current (similar to a switching sram cell). The upside is: There is no static current (unlike the pullup resistor).

Kolja Sulimma

Reply to
comp.arch.fpga

Kolja, I see it differently: A weak keeper has two disadvantages: It is weak, and might be overridden by crosstalk It consumes constant power when the signal is pulled Low.

The > Why not use a weak keeper instead?

Reply to
Peter Alfke

What you have described is a pullup ? Keepers, also called Bus-hold, or PinKeepers (depends on which vendor you are), are snap-action positive feedback 'very light' drivers, and they draw no power in either state. (typically hundreds of uA)

Of course, a disadvantage of that, is the Pin state is now undefined at PowerUP, and that may be a bad thing.

The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis.

-jg

Reply to
Jim Granville

Since Xilinx FPGAs never had weak keepers on the user I/O, I got the nomenclature confused. Sorry. You can of course emulate a weak keeper by using the output driver at its weakest setting, but that may still be too strong in some applications (but not for switch debouncing). BTW, I should have mentioned that the switch must be break-before-make (obviously). Peter Alfke

Reply to
Peter Alfke

The originally-posted circuit and the various minor modifications to it t cover for unknown circumstances...

Reply to
RCIngham

My memory served me poorly, and Ed McGettigan corrected me, thanks:

Virtex outputs have an optional week keeper. as described in the User guide:

PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers, the output can havea weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. For input IBUF) buffers, the input can have either a weak pull-up resistor or a weak pull-down resistor. This feature can be invoked by adding the following possible constraint values to the relevant net of the buffers: =B7 PULLUP =B7 PULLDOWN =B7 KEEPER

Reply to
Peter Alfke

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