Field-Programmable Gate Arrays

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ROM (altsyncram) corruption

Anyone ever seen the contents of an FPGA "rom" (made up of several Stratix M4k rams with one read only port) corrupted?...
11 comments posted 18yrs
posted by cs_posting
11 comments posted 18yrs posted by cs_posting

EDK 9.2 install problem

Hi there, We just received EDK 9.2 but there seems to be an error in the install. I tried to install it and got the err...
2 comments posted 18yrs
posted by pgp
2 comments posted 18yrs posted by pgp

is marked OBSOLETE????

hello all, i would like to ask if you can give me a hint on this problem "ERROR:MDT - Ip ppc405 2.00.a is marked OBSOLET...
1 comments posted 18yrs
posted by lastval
1 comments posted 18yrs posted by lastval

MANIK LwIP port

Hi all, I'm evaluating the MANIK mircoprocess from niktech (www.niktech.com). Following the GettingStarteedGuide, the f...
0 comments posted 18yrs
posted by eejju
0 comments posted 18yrs posted by eejju

Xilinx Parallel Cable IV, API spec

Is the hardware API for "Xilinx Parallel Cable IV Model DLC7" published or does one have to figure that out by traditio...
10 comments posted 18yrs
posted by kgll8ss
10 comments posted 18yrs posted by kgll8ss

Microblaze PLB vs. OPB busses

Now that Microblaze has support for either PLB or OPB, what are the advantages and disadvantages of PLB? I started look...
1 comments posted 18yrs
posted by eric
1 comments posted 18yrs posted by eric

Spartan 3E Starter Kit DDR RAM

Hi All, I've got the Spartan 3E-500 starter kit from Digilent and need to use the DDR ram on the board. I've searched t...
1 comments posted 18yrs
posted by max.batley
1 comments posted 18yrs posted by max.batley

Spartan 3E config

Hi Does anyone know if it is possible to configure a Virtex 4 using a Sparta 3E. I want to connect a Flash memory to th...
1 comments posted 18yrs
posted by maxascent
1 comments posted 18yrs posted by maxascent

Maximum current drive according to datasheet ?!

Hi, I am using a Spartan-3 FPGA and want to drive an I/O pin to the maximum current without damag Iik Input clamp curen...
8 comments posted 18yrs
posted by jidan1
8 comments posted 18yrs posted by jidan1

FIFO interface design

i want to read & write data to/from a fifo placed in fpga. MCU's external bus is connected to the chip. I am using the...
8 comments posted 18yrs
posted by xydarcher
8 comments posted 18yrs posted by xydarcher

P160 Communication Module 3

Hi All , I used the P160 Communication Module 3 add on card for memec xilinx FPGA dev boards a year ago. Where has it go...
5 comments posted 18yrs
posted by niladri1979
5 comments posted 18yrs posted by niladri1979

Non-volatile FPGA in a small package

I am looking for my usual FPGA in a small package. This is a contract design and the customer has a preference to avoid...
22 comments posted 18yrs
posted by gnuarm
22 comments posted 18yrs posted by gnuarm

Custom processor developement issues

Hi all, I'm trying to find a simple way to check the functional correctness of a custom processor/coprocessor/thingy on...
3 comments posted 18yrs
posted by nope
3 comments posted 18yrs posted by nope

did i miss edk 9.2

hi just i quick question: did i miss edk 9.2? there are some service packs for edk 9.2 on the xilinx web site but i can...
5 comments posted 18yrs
posted by u_stadler
5 comments posted 18yrs posted by u_stadler

[Linker script : EDK6.3 -> EDK 8.2] Parse error

Dear I used to EDK 6.3 for multiprocessor system implementation. The system worked fine. But, when I upgraded to EDK 8....
1 comments posted 18yrs
posted by pasacco
1 comments posted 18yrs posted by pasacco