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ISE ignores LOC constraints for BUFGMUX clock buffers

Hi all! I have a simple Spartan3A design where I feed a digital video stream to bank 3 of the device. The idea is to use one of the Left hand clocks in the device to clock data in the IO pads and to the write side of a FIFO and then use a Global clock for the read side and further processing. In order for this to work I have created an AREA_GROUP with all the logic where the Left hand clock occurs, including the BUFGMUX and have assigned a range of slices and clock buffers for this goroup to confine it to the left half of the device, where the clock is supposedly available. Moreover, I have given a specific LOC constraint to the BUFGMUX. All these constraints have been accepted by Translate.

The sad part is that (apart for a breif moment last night) PAR persists in placing the BUFGMUX in one of the global sites in bank 2. This means that the routing from the clock pin (that is one of the LHCLK-pins right near the left hand BUFGMUX) goes across the die and screws ut the timing. I see no reason for this, the clock net is confined to the left hand of the die (verified in FPGA editor) and the specified left hand BUFGMUX is free.

Here is a snippet from the .ucf-file. The dual range AREA_GROUP constraint (commented out below) does not seem to make any differance, I have tried both with and without it. I have also tried giving a range for the LOC constraint, spanning all the left hand BUFGMUX, but no cigar.

# Video input clock buffer, Left hand BUFGMUX X0Y2 INST "fe_mux_inst/vin_clk_buf_inst" LOC = BUFGMUX_X0Y2; # Force VinCLK related logic and clock to left hand side INST "fe_mux_inst" AREA_GROUP = "LeftHandClockedGRP" ; INST "fe_engine_inst" AREA_GROUP = "LeftHandClockedGRP" ; INST "fe_mux_inst/vin_clk_buf_inst" AREA_GROUP = "LeftHandClockedGRP" ; AREA_GROUP "AG_LeftHandClockedGRP" RANGE = SLICE_X0Y0:SLICE_X31Y143 ; #AREA_GROUP "AG_LeftHandClockedGRP" RANGE = SLICE_X32Y8:SLICE_X39Y135 ; AREA_GROUP "AG_LeftHandClockedGRP" RANGE = RAMB16_X0Y0:RAMB16_X0Y15 ;

Time is ticking, the deadline is aproaching, the desperation is building... Any clues out there?

I run ISE 9.1.03i under Windows XP. Synthesis is XST. Clobber me if there are more details I should have included...

/Lars

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noreply.larthe
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As one might expect, I was on a wild goose chase. Please ignore the above post, I had two clock buffers in the block, one called vin_clk_buf_inst and one called vin_clk2_buf_inst. I placed the constraints on vin_clk_buf_inst, that I didn't use and that got optimized away in MAP so I missed that vin_clk2_buf_inst was left without any LOC constraint.

I still can't see why ISE could not figure this topology out by itself. But I guess that is why there are still a need for engineers...

Regards, /Lars

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noreply.larthe

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