I recently read that asynchronous FIFOs have certain clock latency. Can somebody please explain a bit about why is there a latency, or delay, before the data can be read from an asynchronous FIFO? I would also appreciate if you can point me to some reference material.
Latency in asynchronous FIFOs relates to the Empty and Full flags, and really to their trailing edges. Take the Empty flag: It is obviously started by a Read operation, but is terminated by a Write operation. It is of interest only to the Read operation. That means the trailing edge of Empty is generated by one clock, but must be interpreted by the other. That means it has to be re-synchronized, and that takes time. Especially if the careful designer worries about metastability. So the latency you mention is for the trailing edge of the Empty flag (and the Full flag).
Outside Full and Empty, there is no reason for any latency, since (or should I say if) the FIFO is being implemented in a dual-ported RAM, using two independent address counters. You may want to read the FIFO section of the Xilinx Virtex-5 BlockRAM User Guide.