Field-Programmable Gate Arrays

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how to KEEP_HIERARCHY [EDK]

dear In EDK 8.2, I am finding how to set up XST synthesis option "KEEP_HIERARCHY = YES", with no luck. Could someone tel...
1 comments posted 18yrs
posted by pasacco
1 comments posted 18yrs posted by pasacco

gate count calculation in xilinx.

Hi, can anybody help in providing a document or any site relating gate count calculation in xilinx. Thanks & regards sub...
2 comments posted 18yrs
posted by subramanian.2k111
2 comments posted 18yrs posted by subramanian.2k111

New Laptop for work

I am looking at a low end Dell laptop, the Vostro 1500, as a new computer for work. I may supplement this later with a...
10 comments posted 18yrs
posted by gnuarm
10 comments posted 18yrs posted by gnuarm

VHDL language is out of date! Why? I will explain.

Just look at its syntax. It is so archaic that anyone who had any deal with Python will just laugh. Try, say, to create...
41 comments posted 18yrs
posted by psihodelia
41 comments posted 18yrs posted by psihodelia

simulating xilinx block ram with modelsim

hi ich have a problem with a project in ise and modelsim. i used the core generator to create a single port block memor...
16 comments posted 18yrs
posted by u_stadler
16 comments posted 18yrs posted by u_stadler

TI DSP soft core in Xilinx?

I have a V4FX based product and I'd like to have a DSP coprocessor to go with the the powerpc that handles my operating...
4 comments posted 18yrs
posted by cepope
4 comments posted 18yrs posted by cepope

Lattice Semi

Has anyone worked with the Lattice Semiconductor ECP2M series of FPGA? Were the parts easy to get? Also, how is the isp...
23 comments posted 18yrs
posted by Colin.Hankins
23 comments posted 18yrs posted by Colin.Hankins

V4FX: Cannot access EMAC1 of Dual MAC system

I am implementing an PowerPC embedded system in EDK and am trying to use both emac0 and emac1 hard cores of the fpga. I...
6 comments posted 18yrs
posted by JimboD2
6 comments posted 18yrs posted by JimboD2

EDK 9.1 Issues

When working with custom peripherals in EDK, is there a better way to make sure changes to the hardware design take eff...
6 comments posted 18yrs
posted by mdhicks2
6 comments posted 18yrs posted by mdhicks2

Block-ram FIFO in Xilinx

Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Ge...
9 comments posted 18yrs
posted by paraliczb
9 comments posted 18yrs posted by paraliczb

USR_ACCESS_VIRTEX4 usage

Hello all, I would like to use the USR_ACCESS_VIRTEX4 primitive to access an additional bitstream stored in a config fl...
2 comments posted 18yrs
posted by no
2 comments posted 18yrs posted by no

Xilinx ISE Timing Report Question

Hi, I have a question about Xilinx post-P&R static timing reports. I understand most of the constraints listed in the t...
2 comments posted 18yrs
posted by ftpeter
2 comments posted 18yrs posted by ftpeter