Latest threads in Field-Programmable Gate Arrays

synthesizing vqm with parameters with quartus 7.1sp1

Hi, I have a verilog module in my project, which is instantiated in the design 3 times, each time with different parame...

1 18yrs

hershkoy

1 18yrs hershkoy

Altera webpack for Linux?

I noticed that the Xilinx webpack version of ISE now runs in Linux. I seem to recall in the past that the webpack was a...

3 18yrs

jshamlet

3 18yrs jshamlet

Quartus II warning: "pass-through logic has been added"

I tried asking this in the Altera forum, but to no avail. The crux of my question is why the template that Quatus itsel...

12 18yrs

tommy.thorn

12 18yrs tommy.thorn

Coolrunner in system programming - XAPP0058 - viable?

I looked at XAPP0058 which describes some algorithms for in system programming of some Xilinx CPLDs. It appears that th...

50 18yrs

diditgi

50 18yrs diditgi

how to KEEP_HIERARCHY [EDK]

dear In EDK 8.2, I am finding how to set up XST synthesis option "KEEP_HIERARCHY = YES", with no luck. Could someone tel...

1 18yrs

pasacco

1 18yrs pasacco

gate count calculation in xilinx.

Hi, can anybody help in providing a document or any site relating gate count calculation in xilinx. Thanks & regards sub...

2 18yrs

subramanian.2k111

2 18yrs subramanian.2k111

New Laptop for work

I am looking at a low end Dell laptop, the Vostro 1500, as a new computer for work. I may supplement this later with a...

10 18yrs

gnuarm

10 18yrs gnuarm

VHDL language is out of date! Why? I will explain.

Just look at its syntax. It is so archaic that anyone who had any deal with Python will just laugh. Try, say, to create...

41 18yrs

psihodelia

41 18yrs psihodelia

simulating xilinx block ram with modelsim

hi ich have a problem with a project in ise and modelsim. i used the core generator to create a single port block memor...

16 18yrs

u_stadler

16 18yrs u_stadler

TI DSP soft core in Xilinx?

I have a V4FX based product and I'd like to have a DSP coprocessor to go with the the powerpc that handles my operating...

4 18yrs

cepope

4 18yrs cepope

Lattice Semi

Has anyone worked with the Lattice Semiconductor ECP2M series of FPGA? Were the parts easy to get? Also, how is the isp...

23 18yrs

Colin.Hankins

23 18yrs Colin.Hankins

V4FX: Cannot access EMAC1 of Dual MAC system

I am implementing an PowerPC embedded system in EDK and am trying to use both emac0 and emac1 hard cores of the fpga. I...

6 18yrs

JimboD2

6 18yrs JimboD2

EDK 9.1 Issues

When working with custom peripherals in EDK, is there a better way to make sure changes to the hardware design take eff...

6 18yrs

mdhicks2

6 18yrs mdhicks2

Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals for data capture and triggering?

Hi, This is an embarrassing question to be asking - how does one attach signals from the edk design to the chipscope IL...

2 18yrs

andrew.newsgroup

2 18yrs andrew.newsgroup

Block-ram FIFO in Xilinx

Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Ge...

9 18yrs

paraliczb

9 18yrs paraliczb

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