Field-Programmable Gate Arrays

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DDR in spartan 3E

Hi, I use the Spartan display board (spartan 3E 1600), and I try to save a complete video frame (1280*1024) in a DDR. B...
0 comments posted 18yrs
posted by bhb22l
0 comments posted 18yrs posted by bhb22l

Students: where to go for help

Students, Please ask your professor to file a XUP webcase for you, if he/she agrees that yours is a problem that requir...
4 comments posted 18yrs
posted by austin
4 comments posted 18yrs posted by austin

Spartan3E Slave Serial Daisy chain

Hi All, I've got three Spartan3Es daisy chained together in slave serial mode. I'm attempting to configure the 3 device...
7 comments posted 18yrs
posted by ajg112
7 comments posted 18yrs posted by ajg112

Strange VHDL Error

Hi I have a simple package that looks as follows: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.a...
5 comments posted 18yrs
posted by Sascha.Frank23
5 comments posted 18yrs posted by Sascha.Frank23

EDK 8.2 tool : simulator set up

Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following steps: -------------------...
2 comments posted 18yrs
posted by pasacco
2 comments posted 18yrs posted by pasacco

[EDK tool] simulation setup

Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following steps: -------------------...
1 comments posted 18yrs
posted by pasacco
1 comments posted 18yrs posted by pasacco

Programming connection

Looking for ideas to eliminate the programming connector and replace it with pads/contacts on the board. This is both f...
8 comments posted 18yrs
posted by martin.usenet
8 comments posted 18yrs posted by martin.usenet

Xilinx USB cable in Fedora 7

I was wondering about peoples success/failure getting the USB cable working in Fedora 7? I am running 64 bit F7 but am...
1 comments posted 18yrs
posted by junkmail
1 comments posted 18yrs posted by junkmail

Re: Embedded Linux & Code Security

>In FPGAs, configurations can be stored in Flash in an encrypted format that >only the FPGA to be configured has the ke...
1 comments posted 18yrs
posted by jhallen
1 comments posted 18yrs posted by jhallen

newbie to 16v8

Hello group, I'm new to this field and currently learning how 16v8 architecture is designed. Of course, pretty confused...
19 comments posted 18yrs
posted by amit.kohan
19 comments posted 18yrs posted by amit.kohan

SystemACE generation

Hi, I am ajith again. Sorry I forgot to tell you about the error message. The error that I am getting is "Unable to open...
0 comments posted 18yrs
posted by ajith.thamara
0 comments posted 18yrs posted by ajith.thamara

System ACE generation

Hi, I am trying to generate system ACE file in EDK 9.1 . I am trying to combine bitstream with zImage.elf which is used...
0 comments posted 18yrs
posted by ajith.thamara
0 comments posted 18yrs posted by ajith.thamara

Bitslip function in the V5 GTP Transmitter

Is there a bit slip function in the V5 GTP transmitter? Normaly this function is supported in the deserializer devices f...
0 comments posted 18yrs
posted by cpandya
0 comments posted 18yrs posted by cpandya

What the 'c2p' and 'c2o' stand for?

There is a timing diagram comparison between using DCM and not using DCM in http://www.xilinx.com/products/design_resou...
1 comments posted 18yrs
posted by threeinchnail
1 comments posted 18yrs posted by threeinchnail