Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Bitslip function in the V5 GTP Transmitter
Is there a bit slip function in the V5 GTP transmitter? Normaly this function is supported in the deserializer devices for alignment purposes. Thanks. CP
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16 years ago
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What the 'c2p' and 'c2o' stand for?
There is a timing diagram comparison between using DCM and not using DCM in I don't know what the 'c2p' and 'c2o' mean here. The result I found is 'c2p' stands for Military DC-DC Power Supplies and...
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16 years ago
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ROM (altsyncram) corruption
Anyone ever seen the contents of an FPGA "rom" (made up of several Stratix M4k rams with one read only port) corrupted? I have a design where the 80 mhz system clock is coming via the sample clock...
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16 years ago
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EDK 9.2 install problem
Hi there, We just received EDK 9.2 but there seems to be an error in the install. I tried to install it and got the error message "F:idatadrop28.zip.xz error in zipfile". The installer continued after...
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16 years ago
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is marked OBSOLETE????
hello all, i would like to ask if you can give me a hint on this problem "ERROR:MDT - Ip ppc405 2.00.a is marked OBSOLETE" in edk6.2 version. thank you all:)
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16 years ago
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MANIK LwIP port
Hi all, I'm evaluating the MANIK mircoprocess from niktech ( Following the GettingStarteedGuide, the first two examples (banner and ttest) can run happily. But I meet some problem when I compile the...
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16 years ago
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Xilinx Parallel Cable IV, API spec
Is the hardware API for "Xilinx Parallel Cable IV Model DLC7" published or does one have to figure that out by traditional engineering methods ..? (I want to know how to talk to the programmer cable...
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16 years ago
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Microblaze PLB vs. OPB busses
Now that Microblaze has support for either PLB or OPB, what are the advantages and disadvantages of PLB? I started looking at the PLB specification, but I don't yet understand it well enough to have...
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16 years ago
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Spartan 3E Starter Kit DDR RAM
Hi All, I've got the Spartan 3E-500 starter kit from Digilent and need to use the DDR ram on the board. I've searched this group and found lots of references to a port of the opencores DDR controller,...
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16 years ago
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Spartan 3E config
Hi Does anyone know if it is possible to configure a Virtex 4 using a Sparta 3E. I want to connect a Flash memory to the Spartan and set this to be th master. Once configured I want the Virtex 4 that...
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16 years ago
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Maximum current drive according to datasheet ?!
Hi, I am using a Spartan-3 FPGA and want to drive an I/O pin to the maximum current without damag Iik Input clamp curent per I/O pin: ( -0.5 V < VIN < VCCO + 0.5 V): =B1100 mA. So, does that mean I...
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16 years ago
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FIFO interface design
i want to read & write data to/from a fifo placed in fpga. MCU's external bus is connected to the chip. I am using the sync-fifo ip of Altera CycloneII. The data bus and control signal are connected...
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16 years ago
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P160 Communication Module 3
Hi All , I used the P160 Communication Module 3 add on card for memec xilinx FPGA dev boards a year ago. Where has it gone? I cant find it on the avnet memec site. Is it obsolete now? BR Rate
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16 years ago
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Non-volatile FPGA in a small package
I am looking for my usual FPGA in a small package. This is a contract design and the customer has a preference to avoid BGAs. The only leaded part that will fit the board is a 100 pin TQFP. I found a...
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16 years ago
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Custom processor developement issues
Hi all, I'm trying to find a simple way to check the functional correctness of a custom processor/coprocessor/thingy on an FPGA (I'm kindo new at this). The core itself is generated automatically (and...
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16 years ago
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