Field-Programmable Gate Arrays

Split Plane

Hi I am designing an 8 layer board with a Virtex 4 device on it. I will hav 2 solid ground planes and 2 split power pla...

32 comments posted 18yrs

posted by maxascent

32 comments posted 18yrs posted by maxascent

no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02

In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP Starter Kit, the base-system-builder doesn't give me...

2 comments posted 18yrs

posted by ata

2 comments posted 18yrs posted by ata

State machine with stack to implement "subroutines"

Hi All, Playing with the Spartan 3E Starter Kit reference designs, I've found the following "Exercise" in the "Initial...

8 comments posted 18yrs

posted by wzab

8 comments posted 18yrs posted by wzab

xilinx PAR runtime and synplify synth runtime

Hi, I am using Xilinx ISE for PAR (from edf to bit file). and synplify tool for synthesis (to generate edf). Is there s...

1 comments posted 18yrs

posted by vittal.patil

1 comments posted 18yrs posted by vittal.patil

Can i verify RAM content with ISE simulator?

Hello from Diego Italy Another newbie question I'm using XilinxISE 9.2 on a Spartan3 XC3S1500 I would like to implement...

0 comments posted 18yrs

posted by bliscachiocciolinatiscalipuntoit

0 comments posted 18yrs posted by bliscachiocciolinatiscalipuntoit

How to inhibit a timing warning

My Altera Verilog design is clocked at 50MHz (20ns period). Every 60ns, a data word is read and manipulated by combinat...

3 comments posted 18yrs

posted by MikeShepherd564

3 comments posted 18yrs posted by MikeShepherd564

a newbie question

Hello everyone ,I am totally new on this group ,and the subject ,sorry if thoses question are alredy answered. I am ver...

0 comments posted 18yrs

posted by nierveze

0 comments posted 18yrs posted by nierveze

JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...

Hi members, I developed a Spartan-II (xc2s150-5pq208) based card. I also installed Xilinx Flash (xcf01s) there. Unfortu...

4 comments posted 18yrs

posted by irfanfaisalmir

4 comments posted 18yrs posted by irfanfaisalmir

what is the difference between system side XAUI and line side XAUI?

would someone like to give me some explanation about the difference when XAUI work as line side interface or in system i...

0 comments posted 18yrs

posted by cationebox

0 comments posted 18yrs posted by cationebox

Architectural level CMP simulators

Hello everybody, Does anybody have any idea of a multiprocessor simulator. I have worked with uniprocessor architecture...

2 comments posted 18yrs

posted by koustav79

2 comments posted 18yrs posted by koustav79

Spartan 3E 3.3V configuration reverse current situation

Hi, as explained in the note : http://focus.ti.com/lit/an/slva159a/slva159a.pdf .. the use of 3.3V for configuration re...

1 comments posted 18yrs

posted by kislo02

1 comments posted 18yrs posted by kislo02

Initialization of arrays

How does one initialize 'nibbles' in verilog the same way as 'longreg' is initialised .. ? reg [1023:0] longreg = 576'h...

4 comments posted 18yrs

posted by posedge52

4 comments posted 18yrs posted by posedge52

Xilinx EDK 9.2 problems under Centos 5

I installed Centos (linux) 5.1, Xilinx Webpack 9.2i.04, and EDK 9.2.02. However, when i launch 'xpsgui', I see a bunch...

2 comments posted 18yrs

posted by root

2 comments posted 18yrs posted by root

Video processing courses

Hello, I am an FPGA designer and I need to get more general knowledge in the field of video and image processing. Are th...

1 comments posted 18yrs

posted by Karel.Deprez

1 comments posted 18yrs posted by Karel.Deprez

Xilinx XST questions

Hi all i have a series of questions regarding the XST capabilities (read: incapabilities). It all started when i had co...

12 comments posted 18yrs

posted by nkavv

12 comments posted 18yrs posted by nkavv