Field-Programmable Gate Arrays

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Free Seminar on SystemVerilog, Bangalore Jan 5th

Free Seminar on SystemVerilog, Bangalore, Jan 5th mailto: snipped-for-privacy@gmail.com IEEE 1800, SystemVerilog is a m...
0 comments posted 18yrs
posted by cvc.training
0 comments posted 18yrs posted by cvc.training

Where are the LCD or OLED bitmapped displays?

For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps jitter) I need an LCD-backlit or OLED display, 128 x 64...
33 comments posted 18yrs
posted by alfke
33 comments posted 18yrs posted by alfke

Split Plane

Hi I am designing an 8 layer board with a Virtex 4 device on it. I will hav 2 solid ground planes and 2 split power pla...
32 comments posted 18yrs
posted by maxascent
32 comments posted 18yrs posted by maxascent

xilinx PAR runtime and synplify synth runtime

Hi, I am using Xilinx ISE for PAR (from edf to bit file). and synplify tool for synthesis (to generate edf). Is there s...
1 comments posted 18yrs
posted by vittal.patil
1 comments posted 18yrs posted by vittal.patil

Can i verify RAM content with ISE simulator?

Hello from Diego Italy Another newbie question I'm using XilinxISE 9.2 on a Spartan3 XC3S1500 I would like to implement...
0 comments posted 18yrs
posted by bliscachiocciolinatiscalipuntoit
0 comments posted 18yrs posted by bliscachiocciolinatiscalipuntoit

How to inhibit a timing warning

My Altera Verilog design is clocked at 50MHz (20ns period). Every 60ns, a data word is read and manipulated by combinat...
3 comments posted 18yrs
posted by MikeShepherd564
3 comments posted 18yrs posted by MikeShepherd564

a newbie question

Hello everyone ,I am totally new on this group ,and the subject ,sorry if thoses question are alredy answered. I am ver...
0 comments posted 18yrs
posted by nierveze
0 comments posted 18yrs posted by nierveze

Architectural level CMP simulators

Hello everybody, Does anybody have any idea of a multiprocessor simulator. I have worked with uniprocessor architecture...
2 comments posted 18yrs
posted by koustav79
2 comments posted 18yrs posted by koustav79

Initialization of arrays

How does one initialize 'nibbles' in verilog the same way as 'longreg' is initialised .. ? reg [1023:0] longreg = 576'h...
4 comments posted 18yrs
posted by posedge52
4 comments posted 18yrs posted by posedge52

Xilinx EDK 9.2 problems under Centos 5

I installed Centos (linux) 5.1, Xilinx Webpack 9.2i.04, and EDK 9.2.02. However, when i launch 'xpsgui', I see a bunch...
2 comments posted 18yrs
posted by root
2 comments posted 18yrs posted by root