My Altera Verilog design is clocked at 50MHz (20ns period).
Every 60ns, a data word is read and manipulated by combinational logic to give:
one output word which is read after 20ns one output word which is read after 40ns one output word which is read after 60ns
The first output is simply a field of the input and so is certainly available on the next clock.
The second and third outputs involve integer division by nine. This can take longer than 20ns and so Quartus indicates that the timing constraints are not met.
Since the division alone takes more than 20ns, pipelining doesn't help. Even if it did, it seems just a waste of logic to avoid the warning, since the combinational logic actually has enough time to form the result before it's needed.
The second and third results are certainly available by 40ns, but I can't see how to indicate to Quartus that that it can allow more than one clock period for these results.
(I've found it difficult to do relevant searches either in the Quartus documentation or more widely, because I don't know the standard term to describe this problem).
Mike