Where are the LCD or OLED bitmapped displays?

Only 1.4" diagonal, but a nice 128x128 color display:

The integrated controller has some graphics primitives already included (rectangle fill, scrolling etc.), so it is very easy to use (I've tested it with a microcontroller), but the parallel interface should be fast enough to refresh the whole display with 60 Hz from FPGAs, too.

Your clock box sounds interesting. How do you manage 50 ps jitter? Is it possible with your clock box to create e.g. 1.4 GHz and 1.5 GHz with 50% duty cycle and 50 ps jitter? With my first experiments with DDS, jitter can be as worse as 1/main clock frequency.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

50 ps jitter at 1 Hz? That *is* a neat project!

When can I buy one? I was considering getting one of the SRS clock boxes, but yours might do.

John

Thanks, Frank, for the URL. I will investigate. A little pricey, but not out of the question.

Regarding the jitter, I can be more specific in a few weeks, when we have the pre-production version (with the OSRAM display) really working. Until now we have used various form of emulation.

Yes, jitter is the overwhelming issue, and it is 1/fclock coming out of the DDS accumulator, about 2 ns. There is a lot of trickery involved to get the jitter down. The most demanding chore is reducing "wander", i.e. low-frequency components in the jitter spectrum that cannot be filtered out by any analog PLL, but I think we are (almost) there.

We did build a few hundred older boxes for our FAEs some years ago, and they had with a microcontroller), but the parallel interface should be fast enough

n

ems.de

Instead of a display, you could use a program on a PC. There is always a PC or laptop nearby. For example I've implemented a simple GUI and a serial port on the FPGA for my signal generator:

A PLL sounds like a good idea, if you don't want to change the output frequency very fast. Maybe I'll try this with my generator and the internal PLL of the FPGA, if possible.

I wonder how they manage 500 fs (yes, femto seconds) jitter with this cheap chip:

Is this the performance of the DDS, or just the jitter the device adds to the reference clock? But nevertheless, a programmable delay line would be a nice idea for eliminating jitter, without the need for analog circuits. The required delay time could be calculated with the current accumulator value (the bits below the carry).

Thank you, the same to you!

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

C l p a e

ems.de

There are wonderful marketing methods for specifying jitter. Using "RMS" you can divide the "worst-case cycle-to-cycle jitter" value by a factor 14. And worst-case cycle-to-cycle jitter totally ignores the aspect of "wander".

But also: Do not under-estimate the performance of a dedicated "cheap" chip. Have you looked at GPS receiver chips? Astounding !

Gru=DF Peter Alfke

Give us a few months. In the meantime, Stanford Research is a good choice. Amazingly cheap for a very complex traditional design. I'll pack almost everything into one Virtex-5 LXT part. Smaller, simpler and cheaper. Peter

They don't have anything that meets your exact description, but they probably have something you can live with.

The companies that make such displays don't even want to waste time talking to a potential customer if that party isn't likely to buy

100K units.

Digikey show 58, and over a dozen in stock. Highest stock one (also cheapest) shows 1,476 avail - would seem a good target ?

but WHY do you need a 128x64 dot display, for a Clock generator ?

Is there some driving (marketdroid?) need to display the Xilinx logo ;)

For under half the price, you can get a nice 9.22mm H x 4.84mm W Char

16x2, with a nice large Viewing Area 99.00mm L x 23.00mm W

-jg

ar

The original design had a non-backlit 16-character LCD for $4. Now I need twice as much, for 2 independent channels. Also, the crummy display distracted from the quality of the whole box. OLED seemed like a nice solution, but OSRAM went out of that business.

128 x 64 is a slight overkill, but the character generator is free in the Virtex-5, and it allows for some fancy GUI... "How you're gonna keep 'em down on the farm, after they've seen Paree ?" Peter Alfke

Are you planning to reduce the DDS jitter to sub-clock levels on-chip, or are you going to use an external dac-filter-comparator thing?

The on-chip thing could get awfully interesting.

Wander will of course depend on the phase noise of the external master clock. And fpga prop delays will stagger around with tiny temperature fluctuations. Adding thermal insulation and thermal mass to both the fpga and the xo can do remarkable things. We're getting under 30 ps RMS jitter+wander from a delay generator that uses a cheap xo and a Spartan3. A cheap xo will typically have a 1/f sort of jitter corner in the 500 Hz sort of ballpark, hitting a few ns RMS at 1 Hz.

Somebody just quoted us on a 16x2 backlit alphanumeric lcd, 30 mm high, about $7 in small quantity. Do you really need graphics?

John

John, please tell me more about that display. Graphics is just a nice luxury, but backlit or OLED is important.

With "wander" I mean low-frequency jitter: Use a 500 MHz accumulator clock, then use DDS to generate 100.000 001 MHz. There is no way any PLL can completely even out the once-a-second period change. I picked an extreme example, but there are many simpler cases. I was not referring to any instability in the time-base xtal oscillator. That would be on top.

Anyhow, I am glad I asked the original question. I got several good leads. And seem to have created some interest...All on a holiday! Thanks, guys ! Peter

I don't know about the OP, but in my projects, dot matrix means that you can have a "big font" mode and a regular font mode. It also allows more flexible icons.

So is 16x2 enough ?

You could maybe do a Spartan model with the large font 16x 2 I suggested (large chars are much better than smaller ones... ) and a Virtex model, with the FLASH driver, and Animated Xilinx logo reveal, (with full sound effects, too, of course...) etc etc...

What specs would a modern Spartan run to ?

-jg

Does LXT imply that you are using the transceiver outputs to generate a high effective sample frequency?

Thanks, Allan

I still wonder how you get it temperature stabilized if you want to eliminate wander. From my experience with E1 synchronisation systems (I've designed a dpll +/-200ppm in 0.5ppm steps in a Spartan II for that purpose). Just opening the case changed the temperature of the oscillator enough to have the PLL to adjust a few steps.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

The word is that OLED is about to be abandoned. TFT with LED backlighting is probably cheaper to produce.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

A number of displays on the market are still not ROHS compliant, for instance, the nice looking TFT displays advertised by EarthLCD.

John Robbins

One of the bigger troubles in DDS systems isn't the typical wander encountered in oscillators noted by the Allan Variance but the problem of the difference between the instantaneous DDS frequency being different from the idea in the form of a phase error sawtooth function. This phase error will allow a PLL to track a very slow sawtooth curve for most of the sawtooth but will slew across the sharp transition at a rate dependent on the PLL filter. If you have a phase accumulator value that's very close to some 2^n value, the DDR output will be a frequency related to the 2^n value with occasional phase steps to account for that small error. That raw DDS output phase step isn't filtered by a PLL loop function if the occurrence is much slower than the loop filter corner frequency.

For most situations, wander in the Allan Variance sense isn't a problem; it's the phase steps that are a problem. Designing a DDS that provides a fixed frequency with a simple PLL output isn't a problem either if the engineer has the opportunity to choose from a few oscillator values, choosing a frequency ratio that doesn't produce low-frequency error functions of any measurable phase step. It's the general purpose DDS where the frequency can be tuned to 1 Hz off of a subharmonic of the system clock that you'll see that 1 Hz occurrence of a phase step.

We'll have a chance to see Peter manipulate the error to the PLL to both keep the desired frequency to the precision of the input oscillator AND to avoid those phase steps from the inherent sawtooth error.

It's such fun stuff!

- John_H