Split Plane

Hi Jon, There will be an impedance discontinuity at the split. The magnitude of this and whether it matters to your design will depend on the geometry of the stack up and signals; also the rise time of the signals. Why not put the powers on layers 4,5 and make 3 and 6 ground. Then you won't have this problem. HTH., Syms.

No, it doesn't matter. The strange concept of "reference planes" is irrelevent here... how does the signal know what plane you think it's referenced to?

If the power planes are bypassed well enough to make them reliable power sources, then they are AC equipotential with the ground plane, so the signal sees them all as ground. And a small slit in a power plane is essentially invisible for edges slower than a few 10's of picoseconds.

John

John,

You're the only person who I won't directly challenge on your assertion because of your experience in producing quality products while confronting these types of issues directly.

Suffice it to say that "today's common theory" suggests crossing the split in the specified case - like crossing any split - can be the root of crosstalk and EMI issues in addition to signal fidelity issues, just to a lesser extent than for signals on the outside layers.

I'd love to be able to wrap my mind around how crossing this split wouldn't affect the signal in measurable ways, but the things I've been taught - my "faith" perhaps - suggests otherwise. I was once of a mind where crossing the split would be a non-issue but was brought over to the dark side with convincing arguments that tied in mith my more fundamental understanding of transmission line theory.

- John_H

ground============================================================

signal------------------------------------------------------------

power ======================== =================================

whatever ========================================================

OK, there's a slit in the power plane. It's probably about as wide as a normal trace width, call it 8 mils. Let's say the plane-plane spacings are similar distances. Both halves of the split power plane are bypassed to the ground plane by real capacitors and by the considerable large-area plane-plane capacitance.

In order for the trace impedance to change as the trace cruises over the gap, the potential in the middle of the gap would have to be non-zero. But the electric field from the signal trace can hardly penetrate through the gap... that's simple electrostatics. The signal sees uniform ground above, and a slightly lower dielectric constant below, in the gap region. That raises the trace impedance a tiny bit just above the gap, for a tiny distance. The "reference plane" issue is silly, as all the planes are at AC ground.

I've built and TDR's such structures to better than 30 ps resolution. A reflection from such a gap is lost in the normal impedance noise, caused by thickness variations and the glass weave in the board. In the nanosecond domain, it's totally invisible.

On a 2-sided board, a microstrip trace on one side and a cut ground plane on the other,

signal-----------------------------------

ground================== ==============

a narrow slit in the ground plane is still a tiny impedance discontinuity on a TDR plot.

All this "reference plane" stuff is ludicrous. It sure ain't "transmission line theory", it's folklore.

John

It's aimed at getting people to not use *large* slits in their ground planes that *could* turn into significant problems. And you can certainly run simulations and show that -- if you choose a low enough frequency -- current will divert around the slit, like Howard and friends like to draw diagrams of in their books.

The problem is that once everyone nods their heads up and down that, ok, sure, slits in the plane affect what happens electromagnetically, where many people (include me) get off-track in their thinking is in overestimating the detrimental impact of a small slit here or there, when in acutality even significant impedance bumps (say, +/-20% of "nominal" --> 50 ohms nomial going to ~40-60 ohms) of "reasonable" electrical length just don't perturb signals much at all. If they did, simple things like connectors would start becoming Big Deals down in the MHz range rather than the some- to many-GHz range where they usually do.

That being said, I've observed co-workers trying to do things like obtain

60dB isolation at 3GHz on regular old FR-4 circuit boards, and it's not trivial. Without careful design, it's easy to get only, say, 40dB isolation between two traces, even though that's just a *miniscule* amount of energy loss than you're never going to miss it from the original transmitted signal. This is the angle the EMI guys are coming from: While here-a-slit, there-a-slit isn't going to significantly alter your transmitted signal one bit (i.e., your box will still work fine), it can easily cause you to fail EMI testing if you're not careful to make sure those 40-60dB down "sneak" paths never make it out of the box.

I did hear a lecture from one guy who mentioned that if you already have bad enough self-interference (e.g., ground bounce and crosstalk) that your box doesn't work as intended, don't even bother doing an EMI test -- you're already guaranteed to fail. :-)

Have you ever measured the isolation between output channels on your function generators, John? I'd be curious to know the results... :-)

---Joel

The current in the two will be proportional to the capacitance (per unit length), which will depend on the dielectric constant and thickness of the dielectric.

Well, the impedance is the same on both sides, but getting the current where it is needs to go is the problem. As someone else mentioned, bypass capacitors will help. You could put a capacitor across the split between the two power planes. Capacitors to ground from each side should also work. As someone else mentioned, the capacitance of the power plane itself might be enough.

The impedance will be higher, but otherwise it should work.

-- glen

Hi John,

I contend that the flaw in your thinking is that you are _only_ considering "electrostatics", i.e. the electric field and associated capacitance of the system. If you only understand voltage and capacitance, the slot is not a problem for you. In fact, by the reasoning you follow above, a big slot in both planes wouldn't be a problem, and I think this is what you're saying.

Unfortunately, back in the real world, it's called electromagnetism. The magnetic field is important in these systems. The slit will affect the system, changing the loop area for the currents flowing, and the faster the rise time, the more effect you will see due to this added inductance. The effect may or may not be important, but what is important is to consider it.

I'm gonna try this again. I think you do accept that current flows along the trace, so where does the return current flow? Here's a clue. It's in the planes. So, the current is flowing in a loop, right? And a loop has inductance, right? And a big slot in the plane will make the loop area bigger, right? And a bigger area loop has more inductance, right?

However, the two of us have been here before, and I know you don't believe this. I'm posting for the benefit of others who might be caught out by ignoring the magnetic field set up by the currents in the planes and traces so they can make up their own minds. (I suggest SI-list for further reading) Up until recently, regular FPGA I/O circuits were not quick enough for this to be a big problem, but they will be for everyone soon. Maybe not today. Maybe not tomorrow, but soon and for the rest of your life!

I know this won't help, Syms.

p.s. I agree, having a slot in only one plane is nowhere near the same as a slot in both. Here's a link for why a single reference plane with a slot is bad. It's easy to see that another plane can all but short out the return current.

Hi Joel, Good post, thanks! I also would be interested in the answer to the question you pose! Cheers, Syms.

If I may interfere. I believe John is right in stating that all power planes are AC coupled through almost zero impedance. Hence, the return current will not go around the slit but 'jumps along' with the signal. At high frequencies, the trace will act as a microstrip line *.

*All this assuming there is a continuous ground plane.

--
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Hi Nico, If that was _entirely_ true, you wouldn't need bypass caps. That said, I agree they are coupled fairly well, especially at high frequencies, which is why a slot in one of them isn't such a big deal. Probably. I stand by my original assertion that the slot will be an impedance discontinuity. It may well be very small, but we have no details on the board geometry and so we don't know. HTH., Syms.

At least you still believe in conservation of charge, right? Since there is no direct current path across a plane split, you're suggesting that the displacement current (as used in describing current in capacitors) is the full current level found on both sides of that split? Wouldn't the electrostatic effects of this displacement current (given the small dielectric constant/capacitance of FR4) produce a voltage step?

All planes are AC grounded, sure. But to what level? I've watched the effects of signal perturbations on a TDR, too, and I see capacitive or inductive hiccups at poor interfaces. The impedance is the same on both sides of the split but the inductive or capacitive transition can easily be greater than a nanosecond.

Current cannot simply "jump along" in the sense of stopping on one side and starting on the other side of a split without displacement current or induced voltages. While the voltage change will be small due to thee low impedance of the plane, the sub-nanohenry impedance is measurable. If caps are nearby, this impedance is less than if those capacitors were further away but it is still a finite value. There can't be a jump without an induced voltage.

If the charge path for a signal was completely unconstrained and used the entire plane at the transition speeds that are important, the caps would be all we need to worry about, not the splits at all. The continuity of charge is, however, confined to a small area around the signal until these disconnects are encountered. For a signal to propagate, the reflected current must be on both sides of the split; where your "zero impedance" gets lost is in the real voltage generated at this split which has a real impedance associated with it. Ground planes are AC shorts, but this is only an approximation. At the real frequencies, the impedance is measurable - sub-nanohenry, perhaps, but measurable.

- John_H

TDR is not electrostatics. And hand-waving is not measurement.

The edges of the plane gap are glued together by plane-plane capacitance and by the capacitance across the gap itself, which extends across a lot more width than the size of the signal trace. So the "loop area" increase is tiny. Again, the planes are equipotential, all at AC ground, as far as the signal edge is concerned.

I sure wish people would get some copperclad, an xacto knife, and a good TDR, and try some of this stuff, instead or reading books about "black magic."

Goofy. How does he get 15 mV with zero slot length? And what's the slot width? Signal amplitude? And 75 mV of ground noise isn't a signal integrity issue; it might be an emi issue.

John

John - can you recommend any web sites or books that show results of testing PCBs with a TDR? I think that real results would settle these arguments. I can't afford a TDR (and don't know how to use one), so I can't do the tests myself. Any volunteers?

-Dave Pollum

Hi John, Thanks for your reply. I think you read this before and picked holes in it, but for the benefit of other readers, here's a link to a guy who did a similar xacto experiment to the one suggested by John.

Now, the signal in his experiment still gets to the destination kinda ok, but there's a voltage across the slit. This voltage will crosstalk into anything else crossing the slit and will radiate.

There are further experiments here:-

Cheers, Syms.

p.s. Please let me re-iterate that I'm in close agreement with John that, in the OP's case with two adjacent planes only one of which has a slot, it's very likely there will be little if anything to worry about at regular FPGA speeds. Crosstalk and reflections likely won't be a problem. But, multi-gigabit signals are now possible from FPGAs and I advise caution even with differential signals. (Indeed from the first link above, "For cases of a broken ground plane over a solid power plane, or vice versa, there may or may not be a problem depending on several factors including plane spacing.")

With a continuous ground plane and discontinuous power plane, the impedance pretty much doubles across the width of the gap. For wavelengths much (maybe more than 10 times) the gap width the impedance discontinuity should be pretty much not noticed. As the current (or charge, as you say) approaches the gap it spreads out, capacitively couples to the ground plane, crosses the gap, and capacitively couples back to the other power plane. At higher and higher frequencies that process doesn't work as well. Also, that assumes an infinite ground plane.

The effect should be a lot worse without the continuous ground plane the OP specified.

Yes. The question, then, is how big is that voltage relative to the allowed noise in the signal. That depends on the possible current paths (through nearby or not so near bypass capacitors, or interplane capacitance). Without the continuous ground plane the gap impedance is infinite. With the ground plane, it only doubles. That makes a big difference.

Non-infinite planes and the skin effect coming into play.

-- glen

For Pete's sake, he used WIRES. He couldn't even afford an x-acto knife.

Not too surprising, 20 cm away from what appears to be a kilovolt spark gap. It's difficult to make any sort of quantitative extrapolation from this to real circuits.

John

Hi John, Thanks for your resp In Mr. Smith's experiment, the wire crosses a slit in the power plane. I guess he cut the slit with a knife, which I bet he can afford, considering they are cheaper than a Agilent 54845a 'scope! This is a way to get the signal close to a copper-clad plane to simulate the effect of a trace on an adjacent PCB layer to a plane. If the trace is on the opposite face of the copper clad to the plane, the loop area between signal and plane is considerably larger even without the slit, so the slit won't be as big a problem, for a given characteristic impedance of the signal.

John, I think you might have missed this link, but this experiment shows where the current flows. It shows the return current in black and white. (Or maybe yellow!) I'd be especially interested in your comments about this experiment. It shows the signal does not capacitively couple across the slit to any great degree.

This demonstrates susceptibility to electrostatic discharge (ESD). As I'm sure you know, these discharges can easily exceed 1kV. It's important to understand that signals that cross breaks in ground planes are particularly susceptible to ESD.

Thanks, Symon.

Hmm, thinking harder about it, it doesn't necessarily show the lack of current across the gap. But it does show that not all of it couples across. Further experimentation and/or calculation would be necessary to show where the majority of current goes, but the fact that at least some of it follows the path around the slit shows the problem with increased inductance and EMI. Cheers, Syms.

I don't really understand his setup. He claims it simulates a 4-layer board with slits in both the ground and power planes (and who would do THAT?), but doesn't show the copper, if any, on the back side of his test board. And I still think that wire is a poor model for microstrip and an insane model for stripline.

I'd certainly not advocate slitting both the power and ground planes, especially not in the same place; that makes a slotline! My point was that a narrow slit in a power plane is effectively shorted by an adjacent ground plane, by plane-plane capacitance and by explicit bypass caps, and a stripline signal cruising between those planes is barely affected by the slit.

He seems to be demonstrating that current flows in loops where it's forced to flow in loops, which isn't very profound.

I do note that his signal source is made from HC gates, so will have a slow, roughly 7 ns, risetime. That's practically DC for his geometry, so the current flow could have been measured more quantitatively by using dc and measuring the microvolt drops in the copper plane. At serious speeds, and if there were another layer of unbroken plane, things would be different.

All these non-quantitative science projects are sort of irrevelent to the OP's question. Fact is, normal FPGA logic levels can be routed on FR4 multilayer boards, from point to point, with normal care about impedances and termination and obvious crosstalk hazards, without bothering about the effects of vias or crossing power plane slits or "return currents." There's certainly little reason to worry about EMI from a stripline trace sandwiched between bypassed planes.

Things start to get dicey in the 100 ps edge rate ballpark, or for super-speed differential pairs, where more care is required. And routing FPGA clocks, including CCLK, deserves extra care to avoid crosstalk that wiggles rising or falling edges, or diff pair skew for LVDS clocks.

John