Field-Programmable Gate Arrays

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Core Generators...

hi... Im a novice in vhdl based design of fpgas'... I want to know 1. what is the use of core generators? 2. What are x...
10 comments posted 18yrs
posted by krc.1987
10 comments posted 18yrs posted by krc.1987

TechXclusives from Xilinx

Hi all, Does anybody knows where are the web page of "TechXclusives" subject. It seems they've disappeared from Xilinx w...
15 comments posted 18yrs
posted by no_spa2005
15 comments posted 18yrs posted by no_spa2005

Spartan 3 FPGA verification via readback

Hi, I have a custom made FPGA board with Spartan xc3s1000 -4 fg456 on it. There is this strange behaviour of different...
2 comments posted 18yrs
posted by sheikh.m.farhan
2 comments posted 18yrs posted by sheikh.m.farhan

Re: FPGA Project Support

>BALAS009 wrote: >> Dear Sir, >> >> My full project title is to create a dot product of 'n' >> numbers(a0*b0+a1*b1+.......
5 comments posted 18yrs
posted by nico
5 comments posted 18yrs posted by nico

Darnaw1 - PGA FPGA Module

FAQ page page for our Darnaw1 now in place with some of the common questions answered. It's here http://www.enterpoint....
0 comments posted 18yrs
posted by g1
0 comments posted 18yrs posted by g1

video capturing+ filter + vga output

Dear All, I need to do the following: 1. Capturing 10 bit monochrome video 2. Recursive Filtering 3. Display the output...
1 comments posted 18yrs
posted by kurtulmehtap
1 comments posted 18yrs posted by kurtulmehtap

DQS contention with ddr_sdr from Opencores

Hi, Has anyone used the ddr_sdr core (http://www.opencores.org/projects.cgi/web/ddr_sdr/overview) on real hardware ? Th...
4 comments posted 18yrs
posted by sebastien.bourdeauducq
4 comments posted 18yrs posted by sebastien.bourdeauducq

Xilinx Spartan 3 JTAG issues

Hi, I have a XC3S400 based design with an XCF02 and I am finding I can't program the FPGA unless I power cycle it first...
3 comments posted 18yrs
posted by darius
3 comments posted 18yrs posted by darius

help with rising edge matching

Hello, I'm trying to write VHDL code that detects when two signals both rise fro zero to one at the same time. Do you gu...
3 comments posted 18yrs
posted by chongv
3 comments posted 18yrs posted by chongv

Routing Vccint on four-layer PCB

I'm not very experienced at SMT PCB layout, but I'm trying to design a four-layer board with an XC3S50A-4TQG144. I'm us...
8 comments posted 18yrs
posted by eric
8 comments posted 18yrs posted by eric

What is "4-state binary radix" in Modelsim

Hi, For Modelsim XE 6.1e, it says the following on page CR-27 of command reference. I do not understand what is the "4-...
0 comments posted 18yrs
posted by rxjwg98
0 comments posted 18yrs posted by rxjwg98

ASIC verification job info request

I am looking for a reality check. I have 10 years experience doing software verification on EDA tools, in particular ha...
4 comments posted 18yrs
posted by ddilbeck
4 comments posted 18yrs posted by ddilbeck