Field-Programmable Gate Arrays

CPLD Pad File

I am trying to generate a CPLD pad file using a dummy module and ucf. Translate process gives the following error: ERRO...

2 comments posted 18yrs

posted by mailtoakshat

2 comments posted 18yrs posted by mailtoakshat

SRL16x2 in Virtex5

Hello, I have a design where I need a couple of 16-bit shift registers, two bits wide. According to the "Virtex-5 FPGA...

4 comments posted 18yrs

posted by winscatt

4 comments posted 18yrs posted by winscatt

When will Xilinx Webpack and EDK support Vista/64?

I'm pretty annoyed that the iMPACT program (download/program) is unusable under Vista/64. When will this be fixed? Also...

0 comments posted 18yrs

posted by aka

0 comments posted 18yrs posted by aka

Quartus-II 7.2sp1 and Systemverilog Assertion SVA?

I tried synthesizing a Systemverilog-RTL file in Quartus-II 7.2sp1. The synthesis-engine doesn't seem to understand SVA...

1 comments posted 18yrs

posted by aka

1 comments posted 18yrs posted by aka

Using PECL inputs and PLL's in ProASIC Plus.

Hello, I am trying to use the PECL inputs of a ProASIC Plus APA075 device, independently of the PLL blocks. The two PEC...

1 comments posted 18yrs

posted by mlesha

1 comments posted 18yrs posted by mlesha

Two's complement Coregen gone?

Hi, I'm a systems engineer and not the direct FPGA guy, but I'm fairly involved in the implementation of my DSP algorit...

3 comments posted 18yrs

posted by martin.ryba.nospam

3 comments posted 18yrs posted by martin.ryba.nospam

Speed of remote JTAG with Quartus jtagd on linux

I am driving 'jtagd' on a Linux box remotely from a PC to access a ByteBlasterII cable. The client and server PCs are b...

1 comments posted 18yrs

posted by ben

1 comments posted 18yrs posted by ben

Xilinx ISE9.2 iMPACT manual

Is there a complete manual for iMPACT ISE9.2 ? Can't find it. Brad Smallridge AiVision

2 comments posted 18yrs

posted by bradsmallridge

2 comments posted 18yrs posted by bradsmallridge

Chipscope compatible with Synopsis or Cadence sythesise tools?

Hi I have an VHDL core that is sythesizeable with the following tools Synopsys Design Compiler Cadence Encounter RTL Co...

13 comments posted 18yrs

posted by Philipp_G

13 comments posted 18yrs posted by Philipp_G

effect of xray on fpga electronic circuits

Dear All, As an assignment I have to design a CCD Sensor based FPGA digital Camera. However, the Camera will be exposed...

20 comments posted 18yrs

posted by kurtulmehtap

20 comments posted 18yrs posted by kurtulmehtap

CynApps Cynlib

Does anyone have a copy of Forte Design (CynApps) opensource Cynlib? I appreciate if you can send me a copy. -- Amal

5 comments posted 18yrs

posted by akhailtash

5 comments posted 18yrs posted by akhailtash

help definining a secure SMARTCARD CHIP BASED, USB UNIT

Actualy looking to do usb+microcontroller+cpld or usb+ microcontroller ip in fpga LOOKING FOR PARTNERSHIP IN DEVELOPMEN...

0 comments posted 18yrs

posted by ceo

0 comments posted 18yrs posted by ceo

Documentation on Insight VIRTEX-E Reference Board

We are using a number of these boards but do not have the documentation for them and need to make some changes. Any inf...

2 comments posted 18yrs

posted by paul

2 comments posted 18yrs posted by paul

Timing Analyzer hangs

I am using Xilinx ISE 9.02. When I invoke the Timing Analyzer, go to "Analyze" on the pull-down menu, and then further...

0 comments posted 18yrs

posted by internet_checker

0 comments posted 18yrs posted by internet_checker

Basic FPGA question about Reset

Hi I have a very basic question. I have a design that has a clk and reset input. I know that I have to connect the clk...

21 comments posted 18yrs

posted by jey_1453

21 comments posted 18yrs posted by jey_1453