I tried synthesizing a Systemverilog-RTL file in Quartus-II 7.2sp1. The synthesis-engine doesn't seem to understand SVA (systemverilog assertion) syntax.
property prop_x; @ ( posedge clk ) // disable iff (rstn) (!$stable( comb_sm )) |-> ##1 (comb_sm !== BADSTATE); endproperty : prop_x
ap_x: assert property( prop_x );
For now, I've simply put some `ifdef/`endif blocks around the SVA, to conditionally remove it from Quartus-II compile.
Now, I assumed SVA was standardized along with the rest of Systemverilog, and synthesis-tools are supposed to ignore the SVA-constructs -- i.e. ugly `ifdef should not be needed.
Is this understanding correct? For example, does Synopsys Design Compiler and Cadence RTL Compiler require `ifdef blocks around SVA?