Field-Programmable Gate Arrays

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Quartus II Incremental compilation?

The Quartus II handbook says that its Incremental compilation feature has the ability to iterate rapidly during the des...
3 comments posted 18yrs
posted by thakkar.anuja
3 comments posted 18yrs posted by thakkar.anuja

V5-SYSMON : MAX6043 suitable?

Hi all, In UG192 Xilinx proposes to use a MAX6043 Reference IC as a supply for the System Monitor section. But I couldn...
2 comments posted 18yrs
posted by biker
2 comments posted 18yrs posted by biker

gaussian filter in Altera FPGA

Hi all, I'm a new guy in fpga. I need to implement a GMSK in altera fpga. I plan to design a gaussian filter but I don'...
3 comments posted 18yrs
posted by leeyeilan
3 comments posted 18yrs posted by leeyeilan

User inputs into Spartan-3E starter board?

Hey all, I need to input 2 signals into my spartan development board. These will be 5V(+/-10%) signals which I am runni...
2 comments posted 18yrs
posted by jay.wineinger
2 comments posted 18yrs posted by jay.wineinger

Question on FPGA

Does Xilinx have any multicore FPGA ?
2 comments posted 18yrs
posted by jatin.bhateja
2 comments posted 18yrs posted by jatin.bhateja

speed... CORDIC vs. pure arithmetic expression

Hello! I'm student, planing to work with FPGA for my thesis. Totaly unexperienced. Here I'm wondering about the speed....
12 comments posted 18yrs
posted by mfraterBEZ
12 comments posted 18yrs posted by mfraterBEZ

help me about this error

Downloading Bitstream onto the target board ********************************************* impact -batch etc/download.cm...
1 comments posted 18yrs
posted by sunnydath
1 comments posted 18yrs posted by sunnydath

All things ahead, planahead

I am looking at the Xilinx Ahead tools. I was told that there will be a "light" version included in the next release of...
0 comments posted 18yrs
posted by lecroy7200
0 comments posted 18yrs posted by lecroy7200

FPGA Configuration using Multiple PROMs

Hello all, In my recent projects, I was using the V4 device (quite a huge one) and it required two 32MB Platform Flash...
0 comments posted 18yrs
posted by venkat.japan
0 comments posted 18yrs posted by venkat.japan

DCR_INTC usage in EDK - where is SR18804?

I'm trying to get the DCR interrupt controller working in EDK 9.1 with xil_kernel on a V4FX12. Hardware builds fine, bu...
1 comments posted 18yrs
posted by jcc
1 comments posted 18yrs posted by jcc

ieee_ proposed library

Hello all, I am trying to use some of the proposed functions by IEEE which are still awaiting approval. http://www.vhdl...
9 comments posted 18yrs
posted by FPGA.unknown
9 comments posted 18yrs posted by FPGA.unknown

Complex Multiply

I am trying to write a sunction for complex multiplication of 2 complex numbers function complex_multiply(a : signed; b...
8 comments posted 18yrs
posted by thakkar.anuja
8 comments posted 18yrs posted by thakkar.anuja

FPGA's as DSP's

I have heard that FPGA's can have a much larger throughput, dollar per dollar, than a special purpose DSP chip because o...
7 comments posted 18yrs
posted by lm317t
7 comments posted 18yrs posted by lm317t

Help! Micriblase + plbv46_pci in Virtex5

I am connect plbv46_pci(in slavemode) to Micriblase. =F7ut in Plase&Route ISE give warning: WARNING:Route:436 - The rou...
3 comments posted 18yrs
posted by axalay
3 comments posted 18yrs posted by axalay