Hi,
Could anyone explain why FIFO is difficult to implement in FPGA and ASIC? and how is FIFO implemented in FPGA and ASIC.
Thanks, Wei
Hi,
Could anyone explain why FIFO is difficult to implement in FPGA and ASIC? and how is FIFO implemented in FPGA and ASIC.
Thanks, Wei
Where did you read that a FIFO is difficult to implement?
Wei,
According to WHOIS, you're posting from Advanced RISC Machines Ltd. I bet there are several people in your office who can answer that for you.
Perhaps no one in the office will talk to you? Googling fifo+fpga returns
400k hits. Adding I'm+a+little+teapot to the search gets you down to 7.HTH., Syms.
p.s.
p.p.s.
With dual port memory, like many FPGAs and ASICs have it isn't difficult to implement. It isn't for beginners, but it isn't that hard, either.
In FPGA they are implemented with dual port memory and two counters. Also, logic to compare the counters to generate the full and empty status lines.
-- glen
"FIFO" is a broad term and can be either simple or complicated. For starters, a synchronous (single clock), small FIFO should be easy to understand and implement. See, for example:
FIFOs get more complex than that. They can have different clocks for read and write, they can be large and require a dual port memory block, etc.
Start with the simple, advance to the more sophisticated when you need.
Eli
Hi Glen, My favourite FPGA FIFO design is described in XAPP291. The counters' storage elements are part of the dual port RAM. "Their advantage is in using only one clock load." Cheers, Syms.
I'm not planning to start at all. I was asking a question of the original poster.
elements are part of
Pah, I'll beat that for elegance and simplicity....
process(clk,rst) begin one_bit_fifo
I reckon the question was about asynchronous FIFOs and possibly more on the ASIC side, the Full and Empty signals need some care.
Let me throw in my usual tutorial: If you have a dual-ported RAM, designing a synchronous (single-clock) FIFO is trivial. Designing an asynchronous (two independent clocks) FIFO faces the tricky issue of detecting Full and Empty. That means detecting the identity of two counters, which is best done with Gray-coded counters (which in turn makes it difficult to perform arithmetic on them).
The leading edges of Full and Empty are unproblematic, since they are generated by the "proper" clock (Empty is generated by a read operation, and only the read side is interested in the Empty signal) The VERY TRICKY issues are the trailing edges of Full and Empty, since they are caused by the "wrong" clock, and thus require synchronization, and face the UGLY issue of metastability. Enough problems to give you some grey hair... Peter Alfke
Peter Alfke schrieb:
So it looks like you designed quite a lot of those nasty FIFOs . . .
SCNR Falk
Yes, grey hair, but (still) lots of it ! Today is my 20th anniversary at Xilinx. It has been a very good experience, in every respect... Peter
Asynchronous FIFO implementation is also explained in Steve Kilts' Advanced FPGA Design book, although not in great details.
Peter Alfke schrieb:
Congratulations!
Regards Falk
Or just use "coregen". The FIFO's generated by it work pretty darn well. ;)
G.
It's been very good for us too. Many thanks.
-- These are my opinions, not necessarily my employer's. I hate spam.
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