Chipscope compatible with Synopsis or Cadence sythesise tools?

Do you have Xilinx .libs for DC or RC?

Cheers, Jon

There is nothing to synthesize for chipscope icon and ila cores. You instantiate them as black boxes and the netlists for the cores will get pulled in during ngdbuild.

Cheers, Jim

Makes sense, could give that a go! Hope it will work ;)

No, at the moment I am just using the Xilinx stuff. Depends from whom (Xilinx or DC/RC) I could get this libs? hope they are for free. For what exactly do I need them?

I'll admit that if you are doing debugging, then instantiating the cores in your HDL design seems to be the hard way (but maybe that is just me). Have you tried the core inserter instead? It inserts the ILA post synthesis, so it doesn't matter what synthesis tool you use.

If you have tried the inserter, what is it that you prefer about instantiating into the HDL code. I find using the core inserter a quick and flexible process.

Yes I tried using it but it didnt work :D. With the core inserter I never got any data back from the device whereas with the direct instantiation in the code it was working. Rather strange...probably I should give it a go again, i think i have done something wrong with the clock connection!

When using the inserter you may need to set preserve or keep attributes on the signals you want to instrument. Otherwise the optimizations done by your tools may cause problems. The most obvious would be one that is optimized out of the design, but there are more subtle pitfalls.

Also don't forget to set 'trigger same as data' or hook up a real trigger. The first time I set one up in EDK I didn't realize the checkbox for that was off-screen (reachable only with a scrollbar) and didn't understand why I could never trigger...

The Xilinx .libs for DC or RC....is the list of lowlevel Xilinx gates.

When you synthesize you map the rtl to a set of "low" level gates specified by a library. Say you had RTL code

wire [31:0] a,b,c;

assign {carry,c}=a+b;

If the library had a 32bit adder as a low level cell. It would map 1 cell. If the library has 4bits adders as the primitive it maps 4 of those.

The xilinx library would tell the synthesizer which primitives to map to.

Xilinx would normally provide the library. The price is variable. some companies will give it away to potential bulk chip buyers. But since Xilinx has a synthesizer and contracts with Mentor, they are liekly to charge for it.

Xilinx has never charged for synthesis or simulation libraries.

It's been a long time since I've seen any requests for Synopsys synthesis so I had to go check to see if we were still shipping these with each release. I can see that they are still in the 9.2i release tree under $XILINX/synopsys but the files might only be included with the Solaris and Linux installers.

If you don't have them contact your FAE or the hotline and they should be able to get you a copy. BTW, I wouldn't expect to see these around much longer. There must not have been any demand to add Synopsys DC support for Virtex-5 so that is definitely missing.

Ed McGettigan

-- Xilinx Inc.

That is good to hear. I tend to be pestimistic about getting things for free. When NuHorizons finally ships my Spartan 3e kit to me I will look for the files.

I will see how well RC can handle the mapp>>

Yep, someth>

Yes, sometimes the exact signal I want to instrument is not there. And especially, if I stick for example a debug counter in the code that I want to instrument, I have to have it go somewhere or else it will get optimized out before I run the inserter.

I think by RC you mean the Cadence Encounter RTL Compiler. If this is correct then I do not know of any libraries that were ever developed for this tool for FPGA synthesis. My previous comments were with respect to the Synopsys Design Compiler (DC) tool.

I did check the Synopsys DC libraries and there is one for Spartan-3E, but there isn't anything for the newer Spartan-3A families. At one time (early 1990s) there was a very active set of Synopsys DC users and it had good FPGA support, but now the focus is on Synplicity Synplify, Mentor Precision RTL and vendor owned tools.

Ed McGettigan

-- Xilinx Inc.