State machine outputs and tri-state

state

tri-stated

encoding

Check that RDY is not being assigned from another process or concurren assignment.

Check that RDY is not being assigned later in the CP_IN_OUTPUT_DECOD process. That will take precedence.

What happens in simulation?

RDY isn't assigned in another process.

The state machine has 9 states. RDY is assigned in each state, and only tri-stated in sta_idle. Is this wrong? It seems to be the tri-state assignment that throws it.

Ah yes, simulation. As this was supposed to be a simple design, I went straight to hardware and a scope. Thanks.

I'm saying that only because you said you were a beginner, not because of you code =83=BA.

Anyway look at a state machine, it's usually a mishmash of flipflops and logic gates. A tristate is usually a buffer on a bus. In hardware that's 2 different jobs.

So do something like this

signal MY_BUFFER_OUT, MY_BUFFER_IN, MY_BUFFER_CONTROL : std_logic;

MY_BUFFER_OUT

Sorry only half the post went :-) here it is again

Hi Grumps,

You say you=A1=A6re a beginner, so please allow me to offer the one piece of advice that you should never waver from. You are designing hardware, its not software, if you ignore that point you=A1=A6ll join the ranks of people that are giving the industry a bad name with their unstable designs. Always try to imagine the circuit you=A1=A6re describing, and you won=A1=A6t= go far wrong.

I=A1=A6m saying that only because you said you were a beginner, not because of you code =83=BA.

Anyway look at a state machine, it=A1=A6s usually a mishmash of flipflops and logic gates. A tristate is usually a buffer on a bus. In hardware that=A1=A6s 2 different jobs.

So do something like this

signal MY_BUFFER_OUT, MY_BUFFER_IN, MY_BUFFER_CONTROL : std_logic;

MY_BUFFER_OUT

Thanks for the advice and suggestions. Your code is (similar to) what I ended up doing.

It's funny, I've been a hardware engineer for ages, and done FPGA design with Viewdraw schematics many years ago. We now have a VHDL department, so that's our preferred FPGA design route now. But this little project I thought I'd do myself. It works, and only takes 22 slices of a spartan3 (there is a little more to it than this 9-state state machine).

I'm sure I'll be back here with more questions in the future. All the best.

Grumps schrieb:

Hi Grumps, you did no simulation? so how can you be sure that your FSM ever enters sta_2 ?

If you are using an if chain instead of a case for Output decoding you must keep in mind, that the last valid condition sets the output. even a typo can bring you in deep trouble. A case on the other hand has a more straightforward behavior. And the synthesis tool would complain when conditions appear twice.

If RDY is a port there should be no problem with the 'Z' assignment.

I strongly recommend to do a simulation.

and if you like, you can try to rewrite your code like this (if applicable):

case state_cp_in is when sta_idle => RDY

Just a guess! All other state outputs seemed to follow my design. Only the RDY (which was the only one with the 'Z') was errant. What I posted was a cut-down version to make the issue clearer.

Yes, using an if chain. I can't see any typos, and all state conditions are tested.

RDY's an inout port.

I will. Not to check my design, which now works, but to see how the simulator works.

I will try that. Should only take a few minutes.

Thanks :)

I replaced my original process based on lots of if = , with the case method (above). It works! I don't fully understand why though. I simply replaced the "if state_cp_in = " with "when" in my original code so any typos would be preserved.