Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

When are FPGAs the right choice?

I've been programming embedded micros for a long time, and have a decent understanding of hardware. I finally ordered a...
14 comments posted 18yrs
posted by snarflemike
14 comments posted 18yrs posted by snarflemike

setup time not met in Quartus

Hi all, I have a source clock 125MHz (ck125), and it has a derived clock 25MHz(ck25). I find that Quartus generates ck2...
5 comments posted 18yrs
posted by cmchang72
5 comments posted 18yrs posted by cmchang72

floating point arithmetic in vhdl

Hi, is there a library for that , or do I have to code it myself ? Would you be interested in s.th. like that ? Regards...
1 comments posted 18yrs
posted by thorstenkiefer
1 comments posted 18yrs posted by thorstenkiefer

mb-g++ compilation error with EDK 8.2.02i

Specification EDK version:8.2.02i FPGA Board: Virtex II Pro I just upgraded EDK 8.2i to 8.2.02i. In 8.2i compilation of...
0 comments posted 18yrs
posted by priyanthads
0 comments posted 18yrs posted by priyanthads

Spartan 3A starter kit

Hi, Does any one know any examples on the xilinx web site or in the CD (which is sent with the starter kit) that can be...
3 comments posted 18yrs
posted by anas_waris
3 comments posted 18yrs posted by anas_waris

Newbie looking for guidance

Good Afternoon- I posted this to comp.dsp the other day but had someone suggest I post it here. I'm interested in learn...
10 comments posted 18yrs
posted by everphilski
10 comments posted 18yrs posted by everphilski

Redundant Ethernet connection

Hi all, This is somewhat OT, but I am not sure where to ask... In a V4FX based system I need to come up with a way of h...
1 comments posted 18yrs
posted by mbmsv
1 comments posted 18yrs posted by mbmsv

Virtex4FX over-voltage

On a Virtex4FX, if the Vccint was run at 2.5V instead of 1.2v, what problems would someone expect? And after what perio...
4 comments posted 18yrs
posted by morphiend
4 comments posted 18yrs posted by morphiend

Does PC-FPGA communication requires a driver?

Hello, I want to design FPGA-based PC oscilloscope controlled by a user of the PC. I am not sure how to provide communi...
5 comments posted 18yrs
posted by vladimir.v.korostelev
5 comments posted 18yrs posted by vladimir.v.korostelev

'1' or '0' when I/O pin is pulled up

Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am trying to write...
3 comments posted 18yrs
posted by tklau
3 comments posted 18yrs posted by tklau

Vitrex5 JTAG capture and debug

Hi, I'm currently implementing a design with a fairly large amount of static configuration data. It would be good to be...
1 comments posted 18yrs
posted by BertyBooster
1 comments posted 18yrs posted by BertyBooster

Partial reconfiguration reference design?

Dear I heard that there is a good "partial reconfiguration" reference design : Reconfigurable Audio Filter Demo. http:/...
0 comments posted 18yrs
posted by pasacco
0 comments posted 18yrs posted by pasacco

Reed solomon IP core

Hi all, Looking at the Xilinx IP core documentation I found only 2 versions of reed solomon decoder implemented on Virt...
2 comments posted 18yrs
posted by mazouz.nezhate
2 comments posted 18yrs posted by mazouz.nezhate

how to implement this...

Hi lets assume I have two signals, each carrying 8 bits of information. One signal is a so called configuration signal...
10 comments posted 18yrs
posted by Dave
10 comments posted 18yrs posted by Dave

Xilinx ISE and XP home,possible?

Is it possible to install the last version of the free ISE on XP home edition?let me know,please Thanks to you all Diego
2 comments posted 18yrs
posted by bliscachiocciolinatiscalipuntoit
2 comments posted 18yrs posted by bliscachiocciolinatiscalipuntoit