signal generation in VHDL on FPGA.... Check my code please

hi, i have writen a pice of code which should impliment a value on the LEDs of my FPGA development board as the signal 'count' increases. However it is going strait to the ' when others => LEDs

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How do you know it is going straight to that state?

You don't tell us what the CLK signal is ... 1 Hz? 80 MHz? A push button?

- Brian

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Brian Drummond


The case process needs to have 'Count' in the sensitivity list. Also, RST is not needed there, and this is a combinatorial mux.



rossalbi wrote:

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You just need "Count" in the process sensitivity list. If the clock is faster than a few tens of Hz all the LEDs will just glow at varying levels. Unless "Count" is used elsewhere it only needs to be about 3 bits long. If the clock is a reasonable speed, then you might fair better using the upper bits of count as these will toggle slower. You can work out how fast the bits toggle using maths.

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EDs(2), 46=3D>LEDs(7),

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 .

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 .

I think Count should be in the process sensitivity list.

You should get the result you talked about.


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