Field-Programmable Gate Arrays

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Virtex-4 VLX25 DCM problem

Hi all, the following strange thing with Virtex - on the input I have base 24MHz, DCM generates 32MHz internally, and o...
13 comments posted 18yrs
posted by dkolev
13 comments posted 18yrs posted by dkolev

New Release of VPR, Version 5.0 Beta

For those of you interested in research on the development of FPGA CAD and architecture, I am pleased to announce the r...
0 comments posted 18yrs
posted by JonathanScottRose
0 comments posted 18yrs posted by JonathanScottRose

opencores down ?

hi groups I notice that www.opencores.org is down ... the very moment i need jop core... does anybody know if there is a...
2 comments posted 18yrs
posted by rponsard
2 comments posted 18yrs posted by rponsard

Cyclone III and Quartus 7.2sp2

Hi. Analysis and Synthesis for Cyclone III is SO slow.. One my design with about 30000 ALUTs was analysed and synthesed...
9 comments posted 18yrs
posted by drop669
9 comments posted 18yrs posted by drop669

Datasheet on Micron's secure products

Good morning, does anyone know hot to get a datasheet of a Micron's product under NDA? I've an account on Micron.com, b...
4 comments posted 18yrs
posted by enzo_br
4 comments posted 18yrs posted by enzo_br

SiliconBlue enters the FPGA fray

Talk of devices from 1,792 to 15,260 logic blocks, and currents a little under Altera'a MAX IIZ (on a Logic Block basis...
23 comments posted 18yrs
posted by no.spam
23 comments posted 18yrs posted by no.spam

ML523 power module schematics

Does anyone know how I'm supposed to get hold of the ML523 power module schematics? The link on the web site doesn't wor...
3 comments posted 18yrs
posted by enquiries
3 comments posted 18yrs posted by enquiries

Fixing design, leaving BRAMS variable

Hi, currently I am about to finish a design for a Spartan 3 chip. The design uses nearly all slices (98%, 5 slices left...
2 comments posted 18yrs
posted by jboehm
2 comments posted 18yrs posted by jboehm

Xilinx MIG2.0 DDR2 memory controller

Hi, I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It is working well at 200MHz while having calib...
1 comments posted 18yrs
posted by adam0818
1 comments posted 18yrs posted by adam0818