Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx MIG2.0 DDR2 memory controller
Hi, I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It is working well at 200MHz while having calibration problems at 300MHz. after carefully debugging and simulation, I think that...
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16 years ago
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how to Load file data into memory by NIOS II IDE?
Dear all, Please enlighten me on this! Thanks in advance, Sics
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16 years ago
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XC3S50-4VQ100C fpga chip
Hello, Not knowing better, I purchased a couple of these chips and now realize they are 'not simulation ready'. Is there a way for me to use these chips through breadboard or wiring? Or they are only...
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16 years ago
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MicroBlaze MMU support test release now available
Hi, I'm pleased to announce that we have a test release available for MicroBlaze MMU support in the PetaLinux 2.6.20 kernel. You can access it via the front page, just follow the links to the release...
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16 years ago
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802.16d with Xilinx Viterbi Decoder
Does anybody have any experience with programming an 802.16d decoder with the Xilinx Viterbi decoder, as far as how to parameterize the core? I've been beating my head against this and can't quite...
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16 years ago
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I could run my program at DDR Sdram.
Hi, I have written already about this topic. At finally I have configured a DDR SDRAM core for PowerPC so I could read and write from/ to DDR. It supports words, half words and bytes. I have probed it...
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16 years ago
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how to optimize a design for speed
In altera and xilinx how to know that a design works at what frequency. If anyone explains me this one clearly means that will be very much of helpful. I have a design developed long before now i want...
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16 years ago
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question about verilog language constructs
1. In verilog, for continuous assignment, the assignee must be scalar or vector net; for procedure assignment, the assignee cannot be scalar or vector net; then for procedure continuous assignment,...
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16 years ago
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could use some help with verilog/vhdl
I'm having a problem with a state machine written in verilog that I need to get into vhdl. My simulation license only allows vhdl and I can't afford one that will do both. The problems is worse...
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16 years ago
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Anyone to open "FPGA museum" ? Here is first item :)
Hi some things are cute to trash, so if anyone cares for an item that could have its honor place in "FPGA museum", here it is: A Xilinx XC3030 based device manufactured by GRU (== russian CIA). I...
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16 years ago
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Virtex 5
Does anyone have 20-100 pieces of a Xilinx Virtex 5 (XC5VLX85-2FFG676C ) they can spare? I can not wait the factory lead time. Thanks to all that take the time to look into. I also need 140 of the...
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16 years ago
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Spartan-3E + SPI EEPROM
Would this eeprom work as a configuration boot eeprom for Xilinx XC3S500E ..?
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16 years ago
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PCI Timing Contraints ignored
Hi, I have a design for a custom made board with Spartan 3 xc3s1000 on it. There is a SATA controller on the same board. Since this SATA controller uses PCI interface to communicate to the outer...
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16 years ago
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EDK 9.2 MicroBlaze Tutorial and SDRAM TestApp_memory
Hi, I test the EDK 9.2 MicroBlaze Tutorial ( for my Spartan3e Starter Board Rev.D using XPS 9.2.02i. After the bitsream is uploaded, the TestApp_memory is started and got on rs232: -- Entering main()...
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16 years ago
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Bit Error Rate Test
Hi All, I want to implement a BERT test on FPGA. Can anyone give or point me to some good documentation for understanding how BERT test works? Thanks.
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16 years ago
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