In altera and xilinx how to know that a design works at what frequency. If anyone explains me this one clearly means that will be very much of helpful.
I have a design developed long before now i want the same desin to work for the double frequency at what it was working before. So for this what i have to do.
can we synthesize, for and configuration statements in VHDL
Hi, The maximum clock frequency, critical Path etc. are availabe in the static timing report generated by your implementation tool.
Approximations can also be found in the synthesis report (at least in XST). These values might be worsened by the actual Place & Route.
If your old design is now targeted for an actual fpga technology (e.g. migrationg from Spartan2 to Spartan3) you can expect a good increase in the max. possible clock frequency.
Otherwise, if you want to use the same old hardware but double your clock frequency, you have to check the actuaal speed first (static timing report) and, if neccessary, think about redesigning the parts that are identified by the critical path informations. One possible approach is pipelining, if applicable. But sometimes a different coding of the combinatorical part can also be helpful.
For loops and for generate are synthesizable. Configurations are for simulation only.
Have a nice synthesis Eilert
snipped-for-privacy@gmail.com schrieb:
Redesign it with more latency. If start to done takes 4 clock ticks in the old design redo it to use 8 clock ticks (same nS for double frequency). Sometimes I use a step counter and a case statement.
-- Mike Treseler
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