- In verilog, for continuous assignment, the assignee must be scalar or vector net; for procedure assignment, the assignee cannot be scalar or vector net; then for procedure continuous assignment, the assignee can only be scalar or vector of registers. This is very confusing. I can't quite see the logic behind such language design.
- multiple event triggered always block updating same register causing race condition or undefined behavior. e.g.
always @(posedge clock) a = 1'b1; always @(reset) a = 1'b0; If both reset turns high and clock turns high at the same time, what's the result? I see code like this in text books which confuses me.
- my understanding is that always statements is similar to initial forever statements
other than the practical reason always is preferred for looping statements, any catch I don't see?
Thanks a lot!
Fei