Field-Programmable Gate Arrays

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XC3S50-4VQ100C fpga chip

Hello, Not knowing better, I purchased a couple of these chips and now realize they are 'not simulation ready'. Is ther...
6 comments posted 18yrs
posted by fei.liu
6 comments posted 18yrs posted by fei.liu

MicroBlaze MMU support test release now available

Hi, I'm pleased to announce that we have a test release available for MicroBlaze MMU support in the PetaLinux 2.6.20 ke...
0 comments posted 18yrs
posted by jwilliams
0 comments posted 18yrs posted by jwilliams

802.16d with Xilinx Viterbi Decoder

Does anybody have any experience with programming an 802.16d decoder with the Xilinx Viterbi decoder, as far as how to...
0 comments posted 18yrs
posted by paragon.john
0 comments posted 18yrs posted by paragon.john

I could run my program at DDR Sdram.

Hi, I have written already about this topic. At finally I have configured a DDR SDRAM core for PowerPC so I could read...
3 comments posted 18yrs
posted by pbantunez
3 comments posted 18yrs posted by pbantunez

how to optimize a design for speed

In altera and xilinx how to know that a design works at what frequency. If anyone explains me this one clearly means th...
2 comments posted 18yrs
posted by kiransr.ckm
2 comments posted 18yrs posted by kiransr.ckm

question about verilog language constructs

1. In verilog, for continuous assignment, the assignee must be scalar or vector net; for procedure assignment, the assi...
3 comments posted 18yrs
posted by fei.liu
3 comments posted 18yrs posted by fei.liu

could use some help with verilog/vhdl

I'm having a problem with a state machine written in verilog that I need to get into vhdl. My simulation license only a...
2 comments posted 18yrs
posted by danielgkNOSPAM
2 comments posted 18yrs posted by danielgkNOSPAM

Anyone to open "FPGA museum" ? Here is first item :)

Hi some things are cute to trash, so if anyone cares for an item that could have its honor place in "FPGA museum", here...
12 comments posted 18yrs
posted by Antti.Lukats
12 comments posted 18yrs posted by Antti.Lukats

Virtex 5

Does anyone have 20-100 pieces of a Xilinx Virtex 5 (XC5VLX85-2FFG676C ) they can spare? I can not wait the factory lea...
0 comments posted 18yrs
posted by jon
0 comments posted 18yrs posted by jon

Spartan-3E + SPI EEPROM

Would this eeprom work as a configuration boot eeprom for Xilinx XC3S500E ..? http://ww1.microchip.com/downloads/en/Devi...
6 comments posted 18yrs
posted by sky465nm
6 comments posted 18yrs posted by sky465nm

PCI Timing Contraints ignored

Hi, I have a design for a custom made board with Spartan 3 xc3s1000 on it. There is a SATA controller on the same board...
2 comments posted 18yrs
posted by sheikh.m.farhan
2 comments posted 18yrs posted by sheikh.m.farhan

Bit Error Rate Test

Hi All, I want to implement a BERT test on FPGA. Can anyone give or point me to some good documentation for understandin...
5 comments posted 18yrs
posted by mazouz.nezhate
5 comments posted 18yrs posted by mazouz.nezhate

Re: Blast from the past

You might want to also crosspost to comp.arch.fpga. > It's probably been over 20 years since I've used Aplus--was it 19...
8 comments posted 18yrs
posted by wrightjt
8 comments posted 18yrs posted by wrightjt

AES Bitstream Encryption in Virtex-4. How safe it is?

Hi, I need to place my FPGA designs in a safe platform, and I have some questions: 1. Does anybody know whether Virtex-...
27 comments posted 18yrs
posted by maybetooparanoid
27 comments posted 18yrs posted by maybetooparanoid