Field-Programmable Gate Arrays

Temporarely no answer on MEM32 Read request

Hello, At the moment I am designing a PCIe Card with Spartan 3E 1200 -5 and Xilinx PIPE Core. The firmware is almost do...

0 comments posted 18yrs

posted by info

0 comments posted 18yrs posted by info

Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro? ISE isn't seeing it when I try to add new source.

Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro? ISE isn't seeing it when I try to add new source. I...

0 comments posted 18yrs

posted by dale.prather

0 comments posted 18yrs posted by dale.prather

infer block ram with mismatched port width

hi i have a question on how to infer a block ram with mismatched ports. as far as i found out with google and the xilin...

2 comments posted 18yrs

posted by u_stadler

2 comments posted 18yrs posted by u_stadler

Xilinx Pipelined Divider for V5?

Anyone know if Xilinx plans to support the Pipelined Divider for the V5? Is there an equivalent available, buried in som...

0 comments posted 18yrs

posted by vt2001cpe

0 comments posted 18yrs posted by vt2001cpe

Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal without Nios2?

Hi. Got this board. Two questions. 1. Is it possible to use this board as prototype of some USB device without any sold...

6 comments posted 18yrs

posted by drop669

6 comments posted 18yrs posted by drop669

VME 2 Ghz clock generator

Hi, I am loooking for a VME 2 Ghz clock/sync generator board. I find that: -VMETRO XCLK1 -Pentek 6890 Is there a board m...

3 comments posted 18yrs

posted by lpaulo07

3 comments posted 18yrs posted by lpaulo07

Design complexity in Logic cells - Virtex-5 FPGA

Hi, Some IP vendors gives the complexity of the device in terms of "LCs (Logic Cells)". How can I calcuate Logic cells...

5 comments posted 18yrs

posted by muthusnv

5 comments posted 18yrs posted by muthusnv

avnet virtex-5 lx eval kit ddr problem

We have two of these boards (with the LX50 ES), and both failed the DDR memory test with a build from the Base System B...

2 comments posted 18yrs

posted by mikechin2000

2 comments posted 18yrs posted by mikechin2000

Could I develop a new gui using java based on the script language of ChipScope?

I found Chipscope is too difficult to learn for college students, it has too much options. I want to develop a simple g...

8 comments posted 18yrs

posted by wicky.zhang

8 comments posted 18yrs posted by wicky.zhang

Ann: New FPGA beginner's Video guide

Hi all, I have just released a new online Video guide called "The BurchED Getting Started with Xilinx FPGAs Video Guide...

5 comments posted 18yrs

posted by tony

5 comments posted 18yrs posted by tony

BRAM synthesis question

Hi everyone, While trying to build a simple VGA driver, I'm running into trouble getting my video-ram (actually, sample...

14 comments posted 18yrs

posted by boven

14 comments posted 18yrs posted by boven

Matlab, RS-232, Ethernet

Hi, I want to interface matlab with the Xilinx Virtex-II pro board. Intent is to give input from matlab to the FPGA and...

8 comments posted 18yrs

posted by satyam.dwivedi

8 comments posted 18yrs posted by satyam.dwivedi

Virtex-5 FX when ? (III)

Hello Antti, Peter and ..., yep, meanwhile many, many months later - the same question... V5-FX? Thanks and greetings Ud...

5 comments posted 18yrs

posted by WeikEngOff

5 comments posted 18yrs posted by WeikEngOff

vhdl code realization

Hi everyone, I have a issue with fpga design optimization. Can any body explain me What is called "reorder path"? with...

1 comments posted 18yrs

posted by jshrini.vasu

1 comments posted 18yrs posted by jshrini.vasu

its regarding to the Max Frequency in xilinx FPGA

Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my questio...

4 comments posted 18yrs

posted by jshrini.vasu

4 comments posted 18yrs posted by jshrini.vasu