Hi to all,
Is there a way for measuring the length -in terms of time of course- between the blocks in an FPGA? I am trying to do this by using post- route simulations. I wonder if there is a much more efficient way. Up to now I only used Xilinx FPGAs but the information is also welcome for Altera's.
Regards.
Hi Enes load your placed and routed design into the fpga_editor. There you can select signal lines and determine the delays.
Have a nice synthesis Eilert
Enes Erdin schrieb:
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