System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger FPGA

Hi, I cannot give a comment on the usage of better processor or a system with a bigger RAM but I faced a similar situation some time ago when my synthesis on XC2V8000 took some 25-hours to complete on a Multiprocessor machine. For a slightest change in RTL I would wait for a working day to get the bitstream. Later I used Xilinx PlanAhead to floorplan the design and a modification in RTL was sythesized for that individual module and netlist was updated with that frozen floor plan. I reduced our PAR time from 20-hours to just one hour.

Hope this helps

/MH

First off, a multiprocessor/core system won't do you much since the tools do *NOT* support any type of SMP currently. And if you read through the previous discussions about it, you'll see there's a lot of feet dragging with trying to actually implement it as well.

Secondly, from what I've seen here's what you really need: a) a TON of RAM with a 64bit OS to actually support it. b) the fastest processor with the most cache: probably one of the nice big Xeon's.

I have been working on the Core2Duo 6600's for my designs and they've been alright. I have a Xeon w/ 4MB of cache sitting in the lab w/ RH and I have been meaning to get around to testing a build on it, and comparing it between my P4D-3.2Ghz and the Core2Duo 6600. If I ever get around to it, I'll post the results.

-- Mike