Field-Programmable Gate Arrays

Old Mits Dram Datasheet Search

Hi- I'm trying to locate the data sheet for an old 1M x 1 Mitsubishi dram part: MSM41000BJ (70nS) An internet search is...

1 comments posted 18yrs

posted by jflan

1 comments posted 18yrs posted by jflan

CPLD beginner questions

I'm currently using GALs (16V8-18V8-22V10), but my current board requires 4 GALs and I would like to replace them with...

9 comments posted 18yrs

posted by aleksaZR

9 comments posted 18yrs posted by aleksaZR

export to project naigator

I am running some xmp file provided by the manufacturer. The flow for generating bit file was smooth using 7.1 and 8.1...

1 comments posted 18yrs

posted by nbg2006

1 comments posted 18yrs posted by nbg2006

Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from stock

Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from Distributor stock? Am really interested in -...

2 comments posted 18yrs

posted by cpld.fpga.asic

2 comments posted 18yrs posted by cpld.fpga.asic

chipscope analyzer error

I get the following error with chipscope analyzer whenever I do the intialize chain. ERROR: Socket Open Failed. localho...

6 comments posted 18yrs

posted by nbg2006

6 comments posted 18yrs posted by nbg2006

Xilinx EDK - LibGen Error!!!

hi all.... i use xilinx EDK 9.1i. i'm trying to use opb EMAC.... when i run libgen i get this error: "Running system le...

0 comments posted 18yrs

posted by vikram788

0 comments posted 18yrs posted by vikram788

Link for Joining the FPGA/CPLD Design Group on LinkedIn

Link for Joining the FPGA/CPLD Design Group on LinkedIn http://www.linkedin.com/e/gis/56713/3CC3BF77FD22

0 comments posted 18yrs

posted by cpld.fpga.asic

0 comments posted 18yrs posted by cpld.fpga.asic

PLB master : Split bus architecture

Hi, There are three sources for plb master interface. 1) plb_master_single.vhd and plb_master_burst.vhd use a combined...

0 comments posted 18yrs

posted by tejaswyh

0 comments posted 18yrs posted by tejaswyh

DISABLING POWERPC IN VIRTEXII PRO

I have AMIRIX ap1070 board with a xilinx virtex II PRO XC2VP70 . I am trying to use it for network based application ....

2 comments posted 18yrs

posted by nbg2006

2 comments posted 18yrs posted by nbg2006

New Home

Hi, Well, since the Xilinx functional re-organization, I have a new responsibility (here at Xilinx). The bad news(?): I...

3 comments posted 18yrs

posted by austin

3 comments posted 18yrs posted by austin

FPGA to solve the two most annoying problems on usenet - Suggestions Welcome

As you all know, downloading files from usenet leaves you with two sets of files.. The rar files from what you're downl...

13 comments posted 18yrs

posted by skelotar

13 comments posted 18yrs posted by skelotar

Ryhmän sfnet.tori.veneily virallinen kuvaus

*Yleisön pyynnöstä alan julkaisemaan Suomen ydinaavikoitumisen nykytilastamme kertovaa faktaa. M.T.05.05-08. Ilmatietee...

0 comments posted 18yrs

posted by henri.lundberg

0 comments posted 18yrs posted by henri.lundberg

Dram Refresh Controller Tutorial wanted

Hi... I have a desire to interface some dram to a project and was internet searching for some in depth tutorials on ref...

1 comments posted 18yrs

posted by jflan

1 comments posted 18yrs posted by jflan

Trouble programming V4FX40

A working board has been respun to use a FX40 in place of a FX20. For some reason I can't program FPGA on the new board...

22 comments posted 18yrs

posted by mbmsv

22 comments posted 18yrs posted by mbmsv

Altera Quartus Web Edition 8.0 available

I've just had an email from Altera about the availability of Quartus Web Edition 8.0. I'm in the process of downloading...

6 comments posted 18yrs

posted by leon355

6 comments posted 18yrs posted by leon355