Hello,
I have a design on a SX55 that contains of two complex (real
+imaginary) datapaths. I've been trying to debug the code in Chipscope using ILAs before and after my processing block. Both channels are identical in vhdl as they use the same entity. For some reason the output of datapath #1 is showing all zeroes in Chipscope. I checked the design in the FPGA editor and it looks like all of the components and nets are where they should be. I don't have any relevant errors on constraints either.
Please see screenshot linked below:
formatting link
For some reason I'm only getting zero-valued data out of channel 1 and consequently is never being enabled, unlike channel 2... Any ideas?
Thanks,
-Brandon