Hi
I have a bit a problem, I would like to capture the status of 16 registers in my architecture each of them 32 bits long. However, if I try to integrate an Logic Analyzer the maximum datapath that I could use is 256 bits. In my case, I would need 512 bits of data to be transfered between the FPGA and host computer via ILA. Has anyone an idea how I could overcome this limitation so that I could read out the whole information?
Many thanks
I believe you can insert multiple ILA cores, so maybe you can workaround the datapath limitation this way. -Kevin
Another possibility might be to use double data rate. So build a custom core of 256 DDR registers and connect your 512 samples with them. Connect Chipscope with your 256 register, let Chipscope run at twice the clock frequency (and single data rate) you use for your device under test and now you get 2 sets of 256 samples with chipscope.
Regards,
Lorenz
Thanks for your inputs guys, but the thing is that I get now from XST the following error
NUmber of bounded IOBs 484 out of 248 195% (OVERMAPPED)
So it seems that the FPGA just allows me to have a a certain number if input/output information and I cant really read out all the information in the registers...
That error sounds to me to be about external IOs not about FPGA internal connections.
So You do use 484 external Ports within Your toplevel file and do only have something like 248 Pins available? Maybe you should consider multiplexing Your IOs within some wrapper or fully connect Your design to Your module under test.
That is not a chipscope limitation. That is a limitation caused by Your design.
Regards,
Lorenz
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